Abstract: The invention concerns a structure of a readout circuit, formed on a semiconductor substrate (1) of a first type, and intended to measure the charges received from an external charge source (2) external to the substrate (1) according to successive charge integration cycles, said structure comprising: an injection diode configured to inject, into the substrate (1), the charges received from the external charge source (2), a collector diode suitable for collecting, in the substrate (1), at least a portion of the charges injected by the injection diode and for accumulating said charges during an integration cycle, a charge recovery structure (7), configured to recover the charges accumulated in said collector diode, means for initialising the charge recovery structure (7) at the end of each integration cycle, by restoring the electrical potential of said charge recovery structure to an initial potential.

Abstract: The flame-retardant thermoplastic polyurethane elastomer composition includes a thermoplastic polyurethane elastomer, (A) a (poly)phosphate compound represented by general formula (1), (B) a (poly)phosphate compound represented by general formula (3), and (C) silicon dioxide. The composition preferably contains (D) zinc oxide. Symbols n, X1, and p in formula (1) and r, Y1, and q in formula (3) are as defined in the description.

Abstract: The invention concerns a C-MOS photoelectric cell with charge transfer, comprising an embedded photodiode (PPD) likely to be exposed to photons, formed by a doped area of a first type in a substrate of an opposite type, and means for transferring the charges generated by exposing the photodiode to photons to a floating diffusion (FD), and means for reading, on the floating diffusion, a voltage representative of the quantity of charges transferred. This cell is remarkable in that the depletion area of the photodiode junction under zero bias voltage extends essentially through the entire thickness of the doped area of a first type, such that the junction capacitance of said photodiode and the capacitive noise are minimised, and in that, during exposure to photons, the reading is carried out under a condition of equilibrium between the charges generated by photo-conversion and the charges lost by evaporation.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: The invention relates to an active CMOS pixel structure comprising: at least one photoelectric conversion zone (NPD) defined by n-doping of the substrate, said zone accumulating an amount of charge during an exposure to light and comprising a p-doped surface zone (PIN); and at least one MOS transfer transistor (TX), the gate of said transfer transistor (TX) being electrically insulated from the substrate and being used to control transfer of said charge from said photoelectric conversion zone (NPD) to said floating diffusion node (FD), in which the gate of said transfer transistor (TX) partially covers said p-doped surface zone (PIN), and said photoelectric conversion zone (NPD) extends under said gate of said transfer transistor (TX) at least as far as the end of the p-doped surface zone (PIN).

Abstract: The invention concerns a photodiode array, and the method for producing same, comprising—a cathode comprising at least one substrate layer (4) made from a material from the indium phosphide family and one active layer (5) made from a material from the gallium indium arsenide family, and characterised in that the array further comprises at least two sorts of doped regions of the same type at least partially formed in the active layer (5):—first doped regions (3) forming, with the cathode, photodiodes for forming images,—at least one second doped region (8) absorbing excess charge carriers so as to discharge them.

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract: The invention concerns a structure of a CMOS active pixel, comprising a semi-conductive substrate (1) of a first type, at least one first photodiode operating in photovoltaic mode comprising a photovoltaic conversion area (2) defined by a doped area of a second type forming a PN junction with the substrate, said first photodiode re-emitting photoelectric charge carriers collected by the PN junction during the exposure of said first photodiode to a light, at least one second photodiode operating in integration mode and reverse-biased, said second photodiode comprising a charge accumulation area (3) defined by a doped area of the second type forming a PN junction with the substrate, said charge accumulation area being exposed to the charge carriers from the photovoltaic conversion area (2) in order to accumulate such charge carriers.

Abstract: The invention relates to a structure of an active pixel of the CMOS type (1) that comprises: at least one photodiode (10), characterised in that it comprises means for reading any bias voltage in the evolution phase of the photodiode (10) upon exposure.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract: A method and apparatus for unified concurrency control in a Software Transactional Memory (STM) is herein described. A transaction record associated with a memory address referenced by a transactional memory access operation includes optimistic and pessimistic concurrency control fields. Access barriers and other transactional operations/functions are utilized to maintain both fields of the transaction record, appropriately. Consequently, concurrent execution of optimistic and pessimistic transactions is enabled.

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract: The invention relates to an InGaAs photodiode army (101) and to the method for manufacturing same, wherein said array includes: a cathode including at least one indium-phosphide substrate layer (4) and an active gallium-indium arsenide layer (5); and a plurality of anodes (3) at least partially formed in the active gallium-indium arsenide layer by diffusing a P-type dopant, the interaction between an anode (3) and the cathode forming a photodiode. According to said method, an indium-phosphide passivation layer (6) is arranged on the active layer before the diffusion of the P-type dopant forming the anodes (3), and a first selective etching is performed so as to remove, over the entire thickness thereof, an area (10) of the passivation layer (6) surrounding each anode (3).

Abstract: Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.

Abstract: Methods for mapping a function pointer to the device code are presented. In one embodiment, a method includes identifying a function which is executable by processing devices. The method includes generating codes including a first code corresponds to a first processing device and a second code corresponds to a second processing device. The second processing device is architecturally different from the first processing device. The method further includes storing the second code in a byte string such that the second code is retrievable if the function will be executed by the second processing device.

Abstract: The invention relates to an active CMOS pixel structure comprising: at least one photoelectric conversion zone (NPD) defined by n-doping of the substrate, said zone accumulating an amount of charge during an exposure to light and comprising a p-doped surface zone (PIN); and at least one MOS transfer transistor (TX), the gate of said transfer transistor (TX) being electrically insulated from the substrate and being used to control transfer of said charge from said photoelectric conversion zone (NPD) to said floating diffusion node (FD), in which the gate of said transfer transistor (TX) partially covers said p-doped surface zone (PIN), and said photoelectric conversion zone (NPD) extends under said gate of said transfer transistor (TX) at least as far as the end of the p-doped surface zone (PIN).

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

Abstract: An image matrix sensor having a plurality of individual detection structures associated with respective pixels, each individual detection structure including a photodiode having at least one solar cell mode operating range, a first amplifier stage constantly supplied with power and receiving, as an input, a voltage dependent on the voltage of the photodiode which falls within said range; and a second amplifier stage linked to the output of the first amplifier stage and supplied with power in a different manner according to whether or not the first amplifier stage is read.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.