Abstract: Provided is a method of adjusting prefetching operations, the method including setting a prefetching distance, accessing a prefetching-trigger key, determining a target key is outside of the prefetching distance from the prefetching-trigger key, increasing the prefetching distance, and successfully fetching a subsequent target key of a subsequent prefetching-trigger key from a prefetching read-ahead buffer.

Abstract: A system is disclosed. The system may include a processor that may issue a byte level protocol request including a byte address. The system may also include a first storage device and a second storage device. The first storage device and the second storage device may support a cache coherent interconnect protocol, the cache coherent interconnect protocol including a block level protocol and a byte level protocol. The first storage device and the second storage device are included in a redundant array of independent disks (RAID). The first storage device may include a first address range, and the second storage device may include a second address range. The second storage device may provide a RAID address range associated with the first address range and the second address range. A decoder associated with the second storage device may be configured to receive the request from the processor. The decoder may determine that the byte address in the RAID address range is associated with a target address range.

Abstract: A method may include performing, at a computational storage device, using first data stored at the computational storage device, a first computational task of a workload, wherein the performing the first computational task of the workload may include generating second data, transferring, from the computational storage device to a computational device, using an interconnect fabric, the second data, and performing, at the computational device, using the second data, a second computational task of the workload. The transferring the second data may include transferring the second data using a root complex of the interconnect fabric. The transferring the second data may include transferring the second data using a switch of the interconnect fabric. The transferring the second data may include performing a peer-to-peer transfer. The transferring the second data may include performing a direct memory access.

Abstract: An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.

Abstract: Provided is a method for data storage, the method including receiving, by a first storage device, information from a first group of resources for performing a first function on the first storage device using a first implementation, based on the first storage device including the first implementation and being associated with a second group of resources corresponding to the first group of resources.

Abstract: A storage device may include a storage medium, a storage device controller coupled to the storage medium, a host interface coupled to the storage device controller, and an attachable module interface configured to connect an attachable compute module to the storage device controller. The attachable module interface may include a data interface, a side-band interface, and/or a power interface. The attachable module interface may include a connector configured to connect the attachable compute module to the storage device controller. The storage device may include an enclosure having an opening configured to enable the attachable compute module to be connected to the attachable module interface through the opening. The storage device controller may be configured to utilize one or more resources of the attachable compute module. The storage device controller may be configured to communicate with the attachable compute module through one or more command extensions of a storage protocol.

Abstract: A system is described. The system may include a host processor, a host memory connected to the host processor, and a storage device connected to the host processor. An accelerator may communicate with the host processor. The accelerator may produce an output. The accelerator may also include a local memory, which may include a first region and a second region. The first region of the local memory of the accelerator may support a first mode, and the second region of the local memory of the accelerator may support a second mode. The accelerator may store the output of the accelerator in a destination, which may include the host memory, the storage device, the first region of the local memory of the accelerator, or the second region of the local memory of the accelerator.

Abstract: Methods and memory devices are provided. A request is received from a host device at a memory device in a first state. In case that the request is a read request, first data is read from a cache of the memory device based on the read request, and the first data is output to the host device. The cache is loaded with data with the memory device in a second state. In case that the request is a write request, a block of the cache is modified to remove cache data, the cache data and corresponding data from the cache are written to a flash memory of the memory device, and second data is written to the block of the cache based on the received write request.

Abstract: A persistent memory device is disclosed. The persistent memory device may include a cache coherent interconnect interface. The persistent memory device may include a volatile storage and a non-volatile storage. The volatile storage may include at least a first area and a second area. A backup power source may be configured to provide backup power selectively to the second area of the volatile storage. A controller may control the volatile storage and the non-volatile storage. The persistent memory device may use the backup power source while transferring a data from the second area of the volatile storage to the non-volatile storage based at least in part on a loss of a primary power for the persistent memory device.

Abstract: A system is disclosed. The system may include a first device including a first processor, and a second device including a second processor, a memory, a first storage, and a second storage. The first storage may operate at a first speed, and the second storage may operate at a second speed that is slower than the first speed. The second device may be remote relative to the first device. The first device may load a metadata from a memory address in the memory of the second device. The first device may also access a data from the second device based at least in part on the metadata in the memory of the second device.

Abstract: A system may include a receiver to receive a task. The task may include a portion of an algorithm, and may include a task power level and a task precision. The system may also include a circuit including a circuit power level and a circuit precision. The system may include first software to identify the circuit, and second software to assign the task to the circuit to reduce total power. The circuit precision may be greater than the task precision.

Abstract: A storage device includes: protected memory including one or more log pages; non-volatile memory; and a storage controller. The storage controller includes: a command fetcher to receive a data request command associated with data including first metadata and second metadata, and execute the data request command in the non-volatile memory; a logger to identify the second metadata, and log the second metadata in the one or more log pages; and a log page fetcher/eraser to retrieve the second metadata from the one or more log pages in response to a separate command.

Abstract: An accelerator is disclosed. A circuit may process a data to produce a processed data. A first tier storage may include a first capacity and a first latency. A second tier storage may include a second capacity and a second latency. The second capacity may be larger than the first capacity, and the second latency may be slower than the first latency. A bus may be used to transfer at least one of the data or the processed data between the first tier storage and the second tier storage.

Abstract: According to one general aspect, a system may include a plurality of data nodes. Each data node may include either or both of a first storage medium and a second storage medium that is slower than the first storage medium. Each data node may be configured to store a piece data in either the first storage medium or the second storage medium. The system may be configured to store a plurality of copies of an active piece of data within two or more data nodes. A fast copy of the active piece of data may be stored by a first storage medium of a first data node. One or more slow copies of the active piece of data may be stored by respective second storage mediums of one or more respective other data nodes.

Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

Abstract: A method includes receiving, at a controller of a computational storage (CS) device, a request to allocate computational storage to an application of a host device. The request includes a resource set ID associated with the application. The method further includes identifying a memory range within a memory region of the CS device. The method further includes storing, in a data structure associated with the resource set ID, an association between a memory range identifier (ID) of the memory range, the memory region, and an offset within the memory region. The method further includes sending the memory range ID to the host device.

Abstract: A system with an interface for remote memory. In some embodiments, the system includes: an interface circuit having: a first interface, configured to be connected to a processing circuit; and a second interface, configured to be connected to memory, the first interface including a cache coherent interface, and the second interface being different from the first interface.

Abstract: A storage device is disclosed. The storage device may include a volatile storage, a non-volatile storage, and a backup power source configured to provide backup power to the volatile storage. A connector may connect the storage device to a processor. A controller may use the volatile storage as a cache for the non-volatile storage. The controller may copy a data from the volatile storage to the non-volatile storage based at least in part on receiving a signal.

Abstract: A storage device is disclosed. The storage device may comprise storage for input encoded data. A controller may process read requests and write requests from a host computer on the data in the storage. An in-storage compute controller may receive a predicate from the host computer to be applied to the input encoded data. A transcoder may include an index mapper to map an input dictionary to an output dictionary, with one entry in the input dictionary mapped to an entry in the output dictionary, and another entry in the input dictionary mapped to a “don't care” entry in the output dictionary.

Abstract: A method for communicating with a device may include running, at a device, an operating system, communicating, using a first function of an interconnect, with the device, and communicating, using a second function of the interconnect, with the operating system. The operating system may include communication logic, and the communicating with the operating may include communicating with the communication logic. The communication logic may one or more terminal support drivers, and the communicating with the communication logic may include communicating with the one or more terminal support drivers using a terminal application. The terminal application may run on a host. The second function of the interconnect may be configured to operate with a controller. The communicating with the operating system may include communicating with the operating system based on a privilege information. The host may be a management controller.