Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.

Abstract: A non-volatile storage element is provided that includes a control gate, a blocking layer including a ferroelectric material, a charge storage region, and a tunneling layer. The blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A non-volatile storage element including a control gate, a tunneling layer, a charge storage region, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel. The tunneling layer is disposed between the control gate and the charge storage region, the charge storage region is disposed between the tunneling layer and the blocking layer, and the blocking layer is disposed above the semiconductor channel.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack. A memory film is formed within each memory openings. A silicon-germanium alloy layer including germanium at an atomic concentration less than 25% is deposited within each memory opening. An oxidation process is performed on the silicon-germanium alloy layer. A vertical semiconductor channel including an unoxidized remaining material portion of the silicon-germanium alloy layer is formed, which includes germanium at an atomic concentration greater than 50%.

Abstract: A non-volatile storage element is provided that includes a control gate, a blocking layer including a ferroelectric material, a charge storage region, and a tunneling layer. The blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A non-volatile storage element including a control gate, a tunneling layer, a charge storage region, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart among one another by line trenches and a two-dimensional array of memory stack structures and a two-dimensional array of dielectric pillar structures located in the line trenches. Each line trench is filled with laterally alternating sequence of memory stack structures and dielectric pillar structures. Each memory stack structure contains a vertical semiconductor channel, a pair of blocking dielectrics contacting outer sidewalls of the vertical semiconductor channel, a pair of charge storage layers contacting outer sidewalls of the pair of blocking dielectrics, and a pair of tunneling dielectrics contacting outer sidewalls of the pair of charge storage layers.

Abstract: Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the selector device. A wordline sidewall recess process or a wordline sidewall recess with a replacement metal gate process may be used to integrate selector devices with memory cells outside of the memory hole region. By fabricating non-linear selector devices outside of the memory hole region, the area of the memory array may be reduced.

Abstract: A non-volatile memory cell stores 1.5 bits of data in three polarization states. The memory cell may have two ferroelectric layers and three electrodes. The energy bands of the ferroelectric layers are adjusted by providing two of the electrodes with different work functions. The difference in the work functions may be significant, such as at least 0.4-0.6 V or more. Two of the electrodes may have equal or similar work functions. For example, the work functions may be equal within a tolerance of +/?0.1 V. The memory cell can be arranged in various configurations including a FeFET (ferroelectric field effect transistor) and a FeRAM (ferroelectric random access memory). A set of memory cells can be arranged in a string such as a NAND string.

Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.

Abstract: A method is provided that includes forming a first level above a substrate, forming a second level above the first level, and forming a third level above the second level. The first level includes a plurality of first elements having a first minimum pitch, the second level includes a plurality of second elements having a second minimum pitch greater than the first minimum pitch, and the third level includes a plurality of third elements having a third minimum pitch greater than the first minimum pitch. The second elements are disposed above and aligned with a first plurality of the first elements, and the third elements are disposed above and aligned with a second plurality of the first elements.

Abstract: A three-dimensional memory device includes an alternating stack of word lines and insulating layers, vertical semiconductor channels vertically extending through the alternating stack, and a ferroelectric memory material located between each vertical semiconductor channel and the word lines.

Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.

Abstract: A method is provided that includes forming a dielectric material above a substrate, forming a hole in the dielectric material, the hole disposed in a first direction, forming a word line layer above the substrate via the hole, the word line layer disposed in a second direction perpendicular to the first direction, the word line layer including a first conductive material having a first work function, forming a nonvolatile memory material on a sidewall of the hole, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a local bit line in the hole, the local bit line including a second conductive material having a second work function, wherein the first work function is greater than the second work function, and forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer.

Abstract: A vacancy-modulated conductive oxide (VMCO) resistive random access memory (ReRAM) device includes at least one interfacial layer between a semiconductor portion and a titanium oxide portion of a resistive memory element. The at least one interfacial layer includes an oxygen reservoir that can store oxygen atoms during operation of the resistive memory element. The at least one interfacial layer can include an interfacial metal oxide layer, a metal layer, and optionally, a ruthenium layer.

Abstract: Systems and methods for fabricating a non-volatile memory with integrated selector devices (or steering devices) are described. Each memory cell within a memory array may be placed in series with a selector device, such as a diode or other non-linear current-voltage device, in order to reduce leakage currents through unselected memory cells during a memory operation. In some cases, fabricating a selector device within a memory hole region may be difficult due to the dimensions of the selector device. A wordline sidewall recess process or a wordline sidewall recess with a replacement metal gate process may be used to integrate selector devices with memory cells outside of the memory hole region. By fabricating non-linear selector devices outside of the memory hole region, the area of the memory array may be reduced.

Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.

Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.