Patents by Inventor Yanli Zhang

Yanli Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220186071
    Abstract: A heat sensitive aqueous polyurethane dispersion is provided. The heat sensitive aqueous polyurethane dispersion comprises an aqueous polyurethane dispersion; a cationic surfactant; and an anionic surfactant. A method for preparing the heat-sensitive aqueous polyurethane dispersion and a synthetic leather article comprising a film derived from the heat-sensitive aqueous polyurethane dispersion and a coating comprising the heat-sensitive aqueous polyurethane dispersion are also provided.
    Type: Application
    Filed: June 4, 2019
    Publication date: June 16, 2022
    Inventors: Yunlong Guo, Xiangyang Tai, Yanli Feng, Yi Zhang
  • Patent number: 11340432
    Abstract: The present disclosure relates to the field of optical lenses and provides a camera optical lens. The camera optical lens includes, from an object side to an image side: a first lens made of a plastic material; a second lens made of a plastic material; a third lens made of a glass material; a fourth lens made of a glass material; a fifth lens made of a plastic material; a sixth lens made of a plastic material; and a seventh lens made of a plastic material. The camera optical lens satisfies following conditions: 1.50?f1/f?2.50; 1.70?n3?2.20; ?2.00?f3/f4?2.00; 1.00?(R13+R14)/(R13?R14)?10.00; and 1.70?n4?2.20. The camera optical lens can achieve a high imaging performance while obtaining a low TTL.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 24, 2022
    Assignee: AAC Optics Solutions Pte. Ltd.
    Inventors: Yonghua Ji, Lei Zhang, Yanmei Wang, Yanli Xie
  • Publication number: 20220154038
    Abstract: A waterborne polyurethane dispersion is provided. The waterborne polyurethane dispersion is prepared by using a tri-functionality polyether polyol as part of the polyols for forming the prepolymer and a hydrophilic amino siloxane co-chain extender, and can exhibit superior performance properties such as enhanced color fastness, improved low temperature stability, good anti-stickiness, bally flex resistance, anti-abrasion and mechanical properties. A laminated synthetic leather article prepared with said waterborne polyurethane dispersion as well the method for preparing the synthetic leather article are also provided.
    Type: Application
    Filed: August 14, 2019
    Publication date: May 19, 2022
    Inventors: Xiaolian Hu, Chao Zhang, Xiangyang Tai, Yanli Feng, Biao Ma, Ling Ling
  • Publication number: 20220147119
    Abstract: Provided are a display panel, a display device, and an electronic device. The display panel comprises a panel main body. The panel main body comprises a first portion, a second portion and a bendable third portion, and the third portion is located between the first portion and the second portion. A reinforcement layer is provided on a first face of the first portion to make a stiffness of the first portion higher than a stiffness of the third portion.
    Type: Application
    Filed: June 23, 2021
    Publication date: May 12, 2022
    Inventors: Jiaxiang WANG, Binfeng FENG, Yangyang CAI, Yanli WANG, Xinqi LIN, Chao ZHANG, Wei GONG
  • Patent number: 11308685
    Abstract: Various implementations disclosed herein include devices, systems, and methods that dynamically-size zones used in foveated rendering of content that includes text. In some implementations, this involves adjusting the size of a first zone, e.g., a foveated gaze zone (FGZ), based on the apparent size of text from a viewpoint. For example, a FGZ may be increased or decreased in width, height, diameter, or other size attribute based on determining an angle subtended by one or more individual glyphs of the text from the viewpoint. Various implementations disclosed herein include devices, systems, and methods that select a text-rendering algorithm based on a relationship between (a) the rendering resolution of a portion of an image corresponding to a part of a glyph and (b) the size that the part of the glyph will occupy in the image.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Siddharth S. Hazra, William J. Dobbie, Moinul H. Khan, Yanli Zhang, Yohan Rajan, Arthur Y. Zhang
  • Patent number: 11309031
    Abstract: Apparatuses and techniques are described for increasing channel boosting of NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage, VpassL, is applied to designated word lines to create periodic low points or dips in the channel boosting level. A normal pass voltage, Vpass, is applied to other unselected word lines. The low points create barriers to the movement of electrons in the channel toward the selected word line, to prevent the electrons from pulling down the voltage at the channel region which is adjacent to the selected word line. VpassL can be applied to designated word lines at the source and/or drain sides of the selected word line. A control circuit can be configured with various parameters for implementing the techniques.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 19, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ming Wang, Liang Li, Peng Zhang, Yanli Zhang
  • Patent number: 11302716
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: April 12, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Fei Zhou, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang
  • Patent number: 11301969
    Abstract: Some implementations provide improved user experiences on head mounted devices (HMDs) that provide near eye viewing, e.g., HMDs that display distorted images and provide lenses that undistort the images for the user. The images are produced using distortion that is corrected dynamically based on context to conserve device resources. To do so, a context associated with a state of the user, the HMD, or content being viewed on the HMD is tracked during the user experience. For example, the device may predict pupil position, eye state, eye gaze direction, or eye fixation, content type, connection mode, and other context. The device uses the tracked context to determine how to correct distortion for the images at different points during the user experience. For example, new distortion corrections may be computed and used while the user's gaze is moving and previously-determined distortion corrections may be used while the user's gaze is fixed.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 12, 2022
    Assignee: Apple Inc.
    Inventors: Moinul Khan, Simon Fortin-Deschenes, Yanli Zhang, Bennett S. Wilburn, Sterling G. Orsten, Nan Zhu, James Zhou
  • Patent number: 11302714
    Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: April 12, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Satoshi Shimizu, Yanli Zhang
  • Patent number: 11282848
    Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 22, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang, Fei Zhou, Rahul Sharangpani, Adarsh Rajashekhar, Seung-Yeul Yang
  • Patent number: 11280352
    Abstract: A fan cover is configured to be mounted on a housing of a fan module. The fan cover includes a frame having an opening formed therein, a central hub positioned within the opening of the frame, and a plurality of spiral-shaped air guidance members that extend from the central hub to the frame. Gaps between the spiral-shaped air guidance members of the plurality of spiral-shaped air guidance members enable air to flow from the fan module through the fan cover. Each spiral-shaped air guidance member is configured to extend perpendicularly from the central hub and curve towards the frame at an angle with respect to the opening of the frame. Each spiral-shaped air guidance member further has a plurality of openings formed therein to facilitate air flow.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 22, 2022
    Assignee: SCHNEIDER ELECTRIC IT CORPORATION
    Inventor: Yanli Zhang
  • Publication number: 20220068390
    Abstract: Apparatuses and techniques are described for increasing channel boosting of NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage, VpassL, is applied to designated word lines to create periodic low points or dips in the channel boosting level. A normal pass voltage, Vpass, is applied to other unselected word lines. The low points create barriers to the movement of electrons in the channel toward the selected word line, to prevent the electrons from pulling down the voltage at the channel region which is adjacent to the selected word line. VpassL can be applied to designated word lines at the source and/or drain sides of the selected word line. A control circuit can be configured with various parameters for implementing the techniques.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 3, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ming Wang, Liang Li, Peng Zhang, Yanli Zhang
  • Patent number: 11251199
    Abstract: A semiconductor structure includes vertically-alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart from each other by line trenches. Laterally-alternating sequences of semiconductor region assemblies and dielectric pillar structures are located within a respective one of the line trenches. Memory films are located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences. Each of the semiconductor region assemblies includes a source pillar structure, a drain pillar structure, and a channel structure including a pair of lateral semiconductor channels that laterally connect the source pillar structure and the drain pillar structure. The memory films may include a charge storage layer or a ferroelectric material layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: February 15, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Publication number: 20220045091
    Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.
    Type: Application
    Filed: August 5, 2020
    Publication date: February 10, 2022
    Inventors: Zhixin CUI, Satoshi SHIMIZU, Yanli ZHANG
  • Publication number: 20220045092
    Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.
    Type: Application
    Filed: August 5, 2020
    Publication date: February 10, 2022
    Inventors: Zhixin CUI, Satoshi SHIMIZU, Yanli ZHANG
  • Publication number: 20220045090
    Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.
    Type: Application
    Filed: August 5, 2020
    Publication date: February 10, 2022
    Inventors: Zhixin Cui, Satoshi Shimizu, Yanli Zhang
  • Patent number: 11222881
    Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 11, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Kwang-Ho Kim, Johann Alsmeier
  • Publication number: 20210408024
    Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.
    Type: Application
    Filed: June 30, 2020
    Publication date: December 30, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Sarath Puthenthermadam, Yanli Zhang, Huai-yuan Tseng, Peng Zhang
  • Patent number: 11211392
    Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 28, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Sarath Puthenthermadam, Yanli Zhang, Huai-yuan Tseng, Peng Zhang
  • Publication number: 20210358942
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.
    Type: Application
    Filed: May 18, 2020
    Publication date: November 18, 2021
    Inventors: Adarsh RAJASHEKHAR, Rahul SHARANGPANI, Raghuveer S. MAKALA, Fei ZHOU, Yanli ZHANG