Patents by Inventor Yanli Zhang

Yanli Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811431
    Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang
  • Patent number: 10811058
    Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Zhixin Cui, Akio Nishida, Johann Alsmeier, Yan Li, Steven Sprouse
  • Patent number: 10802247
    Abstract: The present disclosure discloses a camera optical lens. The camera optical lens including, in an order from an object side to an image side, a first lens, a second lens having a positive refractive power, a third lens having a positive refractive power, a fourth lens, a fifth lens, and a sixth lens. The first lens is made of plastic material, the second lens is made of plastic material, the third lens is made of plastic material, the fourth lens is made of glass material, the fifth lens is made of plastic material, and the sixth lens is made of plastic material. The camera optical lens further satisfies specific conditions.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 13, 2020
    Assignee: AAC Optics Solutions Pte. Ltd.
    Inventors: Chunhuan Fang, Lei Zhang, Yanmei Wang, Yanli Xie
  • Publication number: 20200312865
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Chun Ge, Jixin Yu, Fabo Yu, Xin Yuan Li, Yanli Zhang
  • Publication number: 20200303397
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: Zhixin CUI, Kiyohiko SAKAKIBARA, Yanli ZHANG
  • Patent number: 10775653
    Abstract: The disclosure discloses an array substrate, a liquid crystal panel, and a process of fabricating the array substrate. The array substrate includes an orientation film, an upper electrode, a lower electrode, and an intermediate electrode located between the upper electrode and the lower electrode, wherein the intermediate electrode is configured to have drive voltage applied thereto when there is zero relative voltage between the upper electrode and the lower electrode, so that an electric field is generated between the intermediate electrode and the lower electrode, and a direction of the electric field is parallel to an orientation direction of the orientation film.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 15, 2020
    Assignees: BOE Technology Group Co., Ltd., Chongqing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Yanli Zhao, Xiaoji Li, Zhi Zhang, He Sun, Xing Dong, Lijun Xiong, Tae Yup Min
  • Patent number: 10777575
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Yanli Zhang
  • Publication number: 20200286903
    Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.
    Type: Application
    Filed: May 21, 2020
    Publication date: September 10, 2020
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Yanli Zhang
  • Publication number: 20200286915
    Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.
    Type: Application
    Filed: May 20, 2020
    Publication date: September 10, 2020
    Inventors: Zhixin Cui, Masatoshi Nishikawa, Yanli Zhang
  • Publication number: 20200286907
    Abstract: A combination of an alternating stack and a memory opening fill structure is provided over a substrate. The alternating stack includes insulating layers and electrically conductive layers. The memory opening fill structure vertically extends through the alternating stack, and includes a memory film, a vertical semiconductor channel, and a core structure comprising a core material. A phase change material is employed for the core material. A volume expansion is induced in in the core material by performing an anneal process that induces a microstructural change within the core material. The volume expansion in the core material induces a lateral compressive strain and a vertical tensile strain within the vertical semiconductor channel. The vertical tensile strain enhances charge mobility in the vertical semiconductor channel, and increases the on-current of the vertical semiconductor channel.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chun GE, Yanli ZHANG, Fei ZHOU, Raghuveer S. MAKALA
  • Publication number: 20200277969
    Abstract: A fan cover is configured to be mounted on a housing of a fan module. The fan cover includes a frame having an opening formed therein, a central hub positioned within the opening of the frame, and a plurality of spiral-shaped air guidance members that extend from the central hub to the frame. Gaps between the spiral-shaped air guidance members of the plurality of spiral-shaped air guidance members enable air to flow from the fan module through the fan cover. Each spiral-shaped air guidance member is configured to extend perpendicularly from the central hub and curve towards the frame at an angle with respect to the opening of the frame. Each spiral-shaped air guidance member further has a plurality of openings formed therein to facilitate air flow.
    Type: Application
    Filed: February 26, 2020
    Publication date: September 3, 2020
    Inventor: Yanli Zhang
  • Publication number: 20200273160
    Abstract: Method and system for displaying one or more regions of interest of an original image. For example, a computer-implemented method for displaying one or more regions of interest of an original image includes: obtaining one or more detection results of one or more first regions of interest, each detection result of the one or more detection results corresponding to one first region of interest of the one or more first regions of interest, each detection result including image information and one or more attribute parameters for their corresponding first region of interest; and obtaining one or more attribute parameter thresholds provided by a user in real time, each attribute parameter threshold of the one or more attribute parameter thresholds corresponding to one attribute parameter of the one or more attribute parameters.
    Type: Application
    Filed: May 23, 2019
    Publication date: August 27, 2020
    Inventors: JIANFENG ZHANG, YANLI SONG, DIJIA WU, YIQIANG ZHAN, XIANG SEAN ZHOU
  • Patent number: 10741128
    Abstract: A dual scan out display system and method for performing the same are described. In one embodiment, the computing system comprises a display and a controller to provide data for separate portions of the display simultaneously using dual scanout.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: August 11, 2020
    Assignee: INTEL CORPORATION
    Inventors: Yanli Zhang, Srikanth Kambhatla
  • Patent number: 10741572
    Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: August 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer Makala, Yanli Zhang, Yao-Sheng Lee
  • Publication number: 20200251488
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 6, 2020
    Inventors: Takaaki IWAI, Makoto KOTO, Sayako NAGAMINE, Ching-Huang LU, Wei ZHAO, Yanli ZHANG, James KAI
  • Publication number: 20200251149
    Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: Yanli ZHANG, Zhixin CUI, Akio NISHIDA, Johann ALSMEIER, Yan LI, Steven SPROUSE
  • Patent number: 10734070
    Abstract: Non-volatile memory strings may include multiple selection devices for coupling memory cell devices to a bit line. Different programming operations may be used to program various individual selection devices in a non-volatile memory cells string. For example, a control circuit may set a threshold voltage of a particular selection device to a value greater than a threshold voltage of another selection device. In another example, the control circuit may program the selection device using an initial sense time. Subsequent to programming the selection device using the initial sense time, the control circuit may program the selection device using a different sense time that is shorter than the initial sense time.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Dengtao Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Zhongguang Xu, Yanli Zhang, Jin Liu
  • Publication number: 20200243498
    Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Inventors: Yanli ZHANG, Kwang-Ho KIM, Johann ALSMEIER
  • Patent number: 10727215
    Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Kwang-Ho Kim, Johann Alsmeier
  • Publication number: 20200232323
    Abstract: Disclosed is a multi-section non-pillar staggered protected roadway for a deep inclined thick coal seam (DITCS) and a method for coal pillar filling between sections. The multi-section non-pillar staggered protected roadway includes a floor, a coal seam, an immediate roof, and a basic roof in a multi-section coal seam, where the floor is disposed below the coal seam, a hydraulic support is disposed in a section between the floor and the immediate roof; a return airway and a transportation roadway are respectively disposed on a left side and a right side of each section; the return airway and the transportation roadway in each section are communicated with each other through a working face; and non-pillar staggered layout is used for a return airway of a next section and a transportation roadway of a current section.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 23, 2020
    Inventors: Panshi XIE, Yingyi ZHANG, Yanli ZHANG, Shuangqi TIAN, Jianjie DUAN