Abstract: A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.

Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers, a vertical layer stack located over the alternating stack, and including multiple levels of vertically interlaced drain select electrodes and drain-select-level insulating layers, a first insulating layer located between the alternating stack and the vertical layer stack, the first insulating layer having a thickness which is greater than a thickness of the respective insulating layers and the respective drain-select-level insulating layers, drain-select-level isolation structures laterally extending along a first horizontal direction such that drain select electrodes located at a same level are laterally spaced apart from each other by the drain-select-level isolation structures, memory openings vertically extending through the vertical layer stack, the first insulating layer, and the alternating stack, and memory opening fill structures located in the memory openings and i

Abstract: The present disclosure discloses gloves capable of automatically starting and stopping a heating function. Each glove includes a glove body; the glove body is internally provided with a heating unit and a control unit, and is at least provided with a first sensing element and a second sensing element; and the first sensing element and the second sensing element are disposed in a spacing manner and are both connected to the control unit. When the first sensing element and the second sensing element sequentially sense that there is a hand signal, the control unit controls the heating unit to perform heating; and when the second sensing element and the first sensing element sequentially sense that the hand signal disappears, the control unit controls the heating unit to stop heating.

Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.

Abstract: The invention relates to a single nucleotide polymorphism (SNP) marker related to a Chinese horse short stature trait. The SNP molecular marker is located at the 501th position of a sequence shown in SEQ ID NO.1, polymorphism is G/A, and the SNP marker corresponds to base pair 18,205,998 on chromosome 8 in a horse. The SNP marker related to the Chinese horse short stature trait and use thereof provided by the present invention have the following advantages that: (1) the molecular marker is not restricted by the age, sex and the like of Chinese horses, is used in early breeding of the Chinese horses, performs accurate screening immediately at birth, and significantly promotes the breeding process of dominant pony varieties of the Chinese horse; (2) a method for detecting SNP of a Chinese horse TBX3 gene is accurate, reliable, and easy to operate.

Abstract: A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.

Abstract: To provide more test data during the manufacture of non-volatile memories and other integrated circuits, machine learning is used to generate virtual test values. Virtual test results are interpolated for one set of tests for devices on which the test is not performed based on correlations with other sets of tests. In one example, machine learning determines a correlation study between bad block values determined at die sort and photo-limited yield (PLY) values determined inline during processing. The correlation can be applied to interpolate virtual inline PLY data for all of the memory dies, allowing for more rapid feedback on the processing parameters for manufacturing the memory dies and making the manufacturing process more efficient and accurate. In another set of embodiments, the machine learning is used to extrapolate limited metrology (e.g., critical dimension) test data to all of the memory die through interpolated virtual metrology data values.

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

Abstract: A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.

Abstract: A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.

Abstract: A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion.

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

Abstract: Various implementations disclosed herein include devices, systems, and methods that dynamically-size zones used in foveated rendering of content that includes text. In some implementations, this involves adjusting the size of a first zone, e.g., a foveated gaze zone (FGZ), based on the apparent size of text from a viewpoint. For example, a FGZ may be increased or decreased in width, height, diameter, or other size attribute based on determining an angle subtended by one or more individual glyphs of the text from the viewpoint. Various implementations disclosed herein include devices, systems, and methods that select a text-rendering algorithm based on a relationship between (a) the rendering resolution of a portion of an image corresponding to a part of a glyph and (b) the size that the part of the glyph will occupy in the image.

Abstract: Apparatuses and techniques are described for increasing channel boosting of NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage, VpassL, is applied to designated word lines to create periodic low points or dips in the channel boosting level. A normal pass voltage, Vpass, is applied to other unselected word lines. The low points create barriers to the movement of electrons in the channel toward the selected word line, to prevent the electrons from pulling down the voltage at the channel region which is adjacent to the selected word line. VpassL can be applied to designated word lines at the source and/or drain sides of the selected word line. A control circuit can be configured with various parameters for implementing the techniques.

Abstract: Some implementations provide improved user experiences on head mounted devices (HMDs) that provide near eye viewing, e.g., HMDs that display distorted images and provide lenses that undistort the images for the user. The images are produced using distortion that is corrected dynamically based on context to conserve device resources. To do so, a context associated with a state of the user, the HMD, or content being viewed on the HMD is tracked during the user experience. For example, the device may predict pupil position, eye state, eye gaze direction, or eye fixation, content type, connection mode, and other context. The device uses the tracked context to determine how to correct distortion for the images at different points during the user experience. For example, new distortion corrections may be computed and used while the user's gaze is moving and previously-determined distortion corrections may be used while the user's gaze is fixed.

Abstract: A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel.

Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex concave sidewall portions.