Patents by Inventor Yanli Zhang

Yanli Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190154971
    Abstract: The present disclosure discloses a camera optical lens. The camera optical lens includes, in an order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens. The camera optical lens further satisfies specific conditions.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 23, 2019
    Inventors: Setsu Sato, Lei Zhang, Yanmei Wang, YanLi Xie
  • Publication number: 20190154964
    Abstract: The present disclosure discloses a camera optical lens. The camera optical lens including, in an order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, and a sixth lens. The first lens is made of glass material, the second lens is made of plastic material, the third lens is made of plastic material, the fourth lens is made of glass material, the fifth lens is made of plastic material, and the sixth lens is made of plastic material. The camera optical lens further satisfies specific conditions.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 23, 2019
    Inventors: Hiroyuki Teraoka, Lei Zhang, Yanmei Wang, Yanli Xie
  • Publication number: 20190154985
    Abstract: The present disclosure discloses a camera optical lens. The camera optical lens includes, in an order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens. The camera optical lens further satisfies specific conditions.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 23, 2019
    Inventors: Setsu Sato, Lei Zhang, Yanmei Wang, YanLi Xie
  • Publication number: 20190154984
    Abstract: The present disclosure discloses a camera optical lens. The camera optical lens includes, in an order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens. The camera optical lens further satisfies specific conditions.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 23, 2019
    Inventors: Kenji Oinuma, Lei Zhang, Yanmei Wang, YanLi Xie
  • Patent number: 10295795
    Abstract: The present disclosure discloses a camera optical lens. The camera optical lens includes, in an order from an object side to an image side, a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens and a seventh lens. The camera optical lens further satisfies specific conditions.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 21, 2019
    Assignee: AAC TECHNOLOGIES PTE. LTD.
    Inventors: Setsu Sato, Lei Zhang, Yanmei Wang, YanLi Xie
  • Patent number: 10298238
    Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 21, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Weicheng Zhang, Huanzhang Huang, Yanli Fan, Roland Sperlich
  • Publication number: 20190148506
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Senaka Krishna KANAKAMEDALA, Yoshihiro KANNO, Raghuveer S. MAKALA, Yanli ZHANG, Jin LIU, Murshed CHOWDHURY, Yao-Sheng LEE
  • Publication number: 20190148392
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Yoshihiro KANNO, Senaka Krishna KANAKAMEDALA, Raghuveer S. MAKALA, Yanli ZHANG, Jin LIU, Murshed CHOWDHURY
  • Patent number: 10288847
    Abstract: The present disclosure discloses a camera optical lens. The camera optical lens including, in an order from an object side to an image side, a first lens, a second lens having a positive refractive power, a third lens having a negative refractive power, a fourth lens, a fifth lens, and a sixth lens. The first lens is made of glass material, the second lens is made of plastic material, the third lens is made of plastic material, the fourth lens is made of plastic material, the fifth lens is made of plastic material, and the sixth lens is made of plastic material. The camera optical lens further satisfies specific conditions.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: May 14, 2019
    Assignee: AAC TECHNOLOGIES PTE. LTD.
    Inventors: Setsu Sato, Lei Zhang, Yanmei Wang, Yanli Xie
  • Patent number: 10290643
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and control gate electrodes located over a substrate, a drain select gate device located above the alternating stack, and a vertical semiconductor channel extending through the alternating stack and through the drain select gate device. The drain select gate device contains a floating gate electrode located between the vertical semiconductor channel and a first drain select gate electrode.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: May 14, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Johann Alsmeier, Yanli Zhang, Peng Zhang
  • Patent number: 10262599
    Abstract: In some examples, a display includes a plurality of display backlight groups, and one or more controller to determine one or more one-dimensional backlight group brightness level adjustments, to determine one or more two-dimensional backlight group brightness level adjustments, and to adjust a brightness of one or more of the backlight groups in response to content of a display image.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: John Lang, Yunhui Chu, Yanli Zhang, Zhiming J. Zhuang
  • Patent number: 10256248
    Abstract: Lower level metal interconnect structures are formed over a substrate with semiconductor devices thereupon. A semiconductor material layer and an alternating stack of spacer dielectric layers and insulating layers is formed over the lower level metal interconnect structures. An array of memory stack structures is formed through the alternating stack. Trenches are formed through the alternating stack such that a staircase region is located farther away from a threshold lateral distance from the trenches, while neighboring staircase regions are formed within the threshold lateral distance from the trenches. Portions of the spacer dielectric layers proximal to the trenches are replaced with electrically conductive layers, while a remaining portion of the alternating stack is present in the staircase region.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: April 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Jixin Yu, Johann Alsmeier, Fumiaki Toyama, Yuki Mizutani, Hiroyuki Ogawa, Chun Ge, Daxin Mao, Yanli Zhang, Alexander Chu, Yan Li
  • Patent number: 10236300
    Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: March 19, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Masanori Tsutsumi, Shinsuke Yada, Sayako Nagamine, Johann Alsmeier
  • Patent number: 10224104
    Abstract: Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murshed Chowdhury, Jin Liu, Yanli Zhang, Andrew Lin, Raghuveer S. Makala, Johann Alsmeier
  • Patent number: 10224407
    Abstract: A trench having a uniform depth is provided in an upper portion of a semiconductor substrate. A continuous dielectric material layer is formed, which includes a gate dielectric that fills an entire volume of the trench. A gate electrode is formed over the gate dielectric such that the gate electrode overlies a center portion of the gate dielectric and does not overlie a first peripheral portion and a second peripheral portion of the gate dielectric that are located on opposing sides of the center portion of the gate dielectric. After formation of a dielectric gate spacer, a source extension region and a drain extension region are formed within the semiconductor substrate by doping respective portions of the semiconductor substrate.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murshed Chowdhury, Andrew Lin, James Kai, Yanli Zhang, Johann Alsmeier
  • Patent number: 10217746
    Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electric
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: February 26, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tae-Kyung Kim, Raghuveer S. Makala, Yanli Zhang, Hiroyuki Kinoshita, Daxin Mao, Jixin Yu, Yiyang Gong, Kazuto Watanabe, Michiaki Sano, Haruki Urata, Akira Takahashi
  • Publication number: 20190035803
    Abstract: A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions and convex sidewall portions.
    Type: Application
    Filed: October 16, 2017
    Publication date: January 31, 2019
    Inventors: Yanli ZHANG, Masanori TSUTSUMI, Shinsuke YADA, Sayako NAGAMINE, Johann ALSMEIER
  • Patent number: 10192878
    Abstract: Sacrificial memory opening fill structures are formed through an alternating stack of insulating layers and sacrificial material layers. A drain select level isolation trench extending through drain select level sacrificial material layers is formed employing a combination of a photoresist layer including a linear opening and a pair of rows of sacrificial memory opening fill structures as an etch mask. Sacrificial spacers are formed on sidewalls of the drain select level isolation trench. A drain select level isolation dielectric structure is formed in a remaining volume of the drain select level isolation trench. The sacrificial memory opening fill structures are replaced with memory stack structures. The sacrificial material layers and the sacrificial spacers are replaced with a conductive material to form electrically conductive layers and conductive connector spacers.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: January 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masanori Tsutsumi, Shinsuke Yada, Yanli Zhang
  • Publication number: 20180374866
    Abstract: A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Raghuveer S. MAKALA, Senaka Krishna KANAKAMEDALA, Yanli ZHANG, Yao-Sheng LEE
  • Publication number: 20180366482
    Abstract: A three-dimensional memory device can be formed by first forming an alternating stack of insulating layers and stack level spacer material layers over a substrate. The stack level spacer material layers can be formed as, or are subsequently replaced with, stack level electrically conductive layers. A bottommost insulating spacer layer is formed with recesses that form grooves that are laterally spaced apart. Drain select level electrically conductive layers are formed over protruding portions and within the grooves of the bottommost insulating spacer layer by anisotropic deposition and isotropic etch back of a conductive material. Additional insulating spacer layers may be formed by anisotropic deposition of an insulating material. Additional drain select level electrically conductive layers can be formed by anisotropic deposition and isotropic etch back of additional conductive material.
    Type: Application
    Filed: June 20, 2017
    Publication date: December 20, 2018
    Inventors: Fei Zhou, Rahul Sharangpani, Yanli Zhang, Raghuveer S. Makala, Senaka Krishna Kanakamedala