Abstract: A memory includes a transistor and a magnetic tunnel junction (MTJ) storage element, a bottom electrode of the MTJ storage element is electrically connected to a drain electrode of the transistor using a conduction structure, wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers, the conduction structure includes a first conduction part, and the first conduction part includes a first metal wire, a second metal wire, and a first via hole, the wiring layers comprise a first wiring layer, a second wiring layer, and a third wiring layer, the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer.

Abstract: A memory includes a storage array, at least one source line, at least one word line, and at least one bit line. The storage array includes a plurality of gate-all-around field-effect transistors. The at least one word line is connected to gates of the plurality of gate-all-around field-effect transistors. The at least one source line is connected to sources of the plurality of gate-all-around field-effect transistors. The at least one bit line is connected to drains of the plurality of gate-all-around field-effect transistors. A material of a nanowire of the gate-all-around field-effect transistor is silicon germanium (SiGe). For a next-generation logic process (for example, a GAA process), a storage array including a gate-all-around field-effect transistor manufactured by using a same process as a logic process is used in a memory so that the memory can be compatible with the logic process.

Abstract: A train compartment brake control method includes: acquiring the number of train compartments of a current train; acquiring the number and type of a current train compartment; and on the basis of a train brake instruction and the number of train compartments of the current train, calculating a braking force of the current train compartment, and performing brake control on the current train compartment. The technical solution described in the present application is applicable to a train having any number of train compartments. The above method acquires the number of train compartments of a train in real time, calculates the braking force required by each train compartment according to the number and type of a current train compartment, and performs brake control on the train.

Abstract: A compound having anti-aging and discoloration resistance effects and a preparation method therefor are provided. The structure of the compound is represented by formula (I). The compound provides longer-lasting anti-aging performance, and has discoloration resistance. The compound may be used as an anti-aging agent in rubber products, especially rubber tires, and can prevent the aging and deterioration of rubber products or rubber tires due to light, heat, oxygen, and fatigue, during use.

Abstract: Disclosed are a railway vehicle and a storage battery circuit breaker box thereof. The storage battery circuit breaker box comprises a circuit breaker box body, where mounting bases are arranged on side walls of the circuit breaker box body; a mounting positioning plate and a waterproof protection plate are fixedly mounted on a surface of one side of the circuit breaker box body; the mounting positioning plate is of a rectangular annular structure with an opening provided in the bottom thereof; the waterproof protection plate is located at the inner side of the mounting positioning plate; the waterproof protection plate is of a door-shaped structure; and perspective windows and a switch mounting hole are provided at the circuit breaker box body. The circuit breaker box can be mounted inside a vehicle body, maintenance by maintenance personnel outside the vehicle is facilitated, and the sealing requirements can also be met.

Abstract: A memory and an electronic device are provided. The memory includes a storage element (10), a first transistor (21), a second transistor (22), a first bit line (BLA), and a second bit line (BLB). The storage element (10) is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor (21) and the second transistor (22), and the first transistor (21) and the second transistor (22) are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.

Abstract: A field-effect transistor structure includes a semiconductor substrate, a metal gate, a metal trench for source, a metal trench for drain, an etching-stop layer, and a gate contact, the etching-stop layer is overlaid on the metal trench for source and the metal trench for drain. The gate contact is above an active region.

Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. Apart that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

Abstract: This application provides a memory including a transistor and an MTJ storage element; a bottom electrode of the MTJ storage element is electrically connected to a drain electrode of the transistor by using a conduction structure; wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers; the conduction structure includes a first conduction part, and the first conduction part includes a first metal wire, a second metal wire, and a first via hole; the wiring layers comprise a first wiring layer, a second wiring layer, and a third wiring layer; the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer.

Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.

Abstract: A train compartment brake control method comprises the following steps: acquiring the number of train compartments of a current train; acquiring the number and type of a current train compartment; and on the basis of a train brake instruction and the number of train compartments of the current train, calculating a braking force of the current train compartment, and performing brake control on the current train compartment. The technical solution described in the present application is applicable to a train having any number of train compartments. The above method acquires the number of train compartments of a train in real time, calculates the braking force required by each train compartment according to the number and type of a current train compartment, and performs brake control on the train.

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

Abstract: There is set forth herein a semiconductor device fabricated on a bulk wafer having a local buried oxide region underneath a channel region of a MOSFET. In one embodiment the local buried oxide region can be self-aligned to a gate, and a source/drain region can be formed in a bulk substrate. A local buried oxide region can be formed in a semiconductor device by implantation of oxygen into a bulk region of the semiconductor device followed by annealing.

Abstract: To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

Abstract: Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract: To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

Abstract: A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).