Abstract: A finFET device according to some examples herein may include an active gate element above an active fin element and a dummy fin element that partially breaks the active gate element. In another example, a dummy gate element adjacent to an active gate element contains a dummy fin element that partially breaks the dummy gate element. In another example, a first dummy fin element partially breaks an active gate element and a second dummy fin element partially breaks a dummy gate element. In another example, the dummy fin element is of the same material as the active fin element. In another example, the dummy fin element partially breaks a gate element but does not extend to the substrate like the active fin element.

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract: A method of fabrication of a device includes performing a gate cut to cut a gate line to create a first gate region and a second gate region. The method further includes depositing a conductive material to form a conductive jumper structure to connect the first gate region and the second gate region.

Abstract: A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region.

Abstract: In a particular aspect, an integrated circuit includes a first gate structure coupled to a first fin field effect transistor (FinFET) device. The integrated circuit includes a second gate structure coupled to a second FinFET device. The first gate structure and the second gate structure are separated by a dielectric region. The integrated circuit further includes a metal contact having a first surface that is in contact with the dielectric region, the first gate structure, and the second gate structure.

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract: Integrated circuits that have a FinFET and methods of fabricating the integrated circuits are provided herein. In an embodiment, a method of fabricating an integrated circuit having a FinFET includes providing a substrate comprising fins. The fins include semiconductor material. A first metal oxide layer is formed over sidewall surfaces of the fins. The first metal oxide layer includes a first metal oxide. The first metal oxide layer is recessed to a depth below a top surface of the fins to form a recessed first metal oxide layer. The top surface and sidewall surfaces of the fins at a top portion of the fins are free from the first metal oxide layer. A gate electrode structure is formed over the top surface and sidewall surfaces of the fins at the top portion of the fins. The recessed first metal oxide layer is recessed beneath the gate electrode structure.

Abstract: A semiconductor fin includes a channel region. A gate-stressor member, formed of a metal, extends transverse to the fin and includes gate surfaces that straddle the fin in the channel region. The gate-stressor member has a configuration that includes a partial cut spaced from the fin by a cut distance. The configuration causes, through the gate surfaces, a transverse stress in the fin, having a magnitude that corresponds to the cut distance. Transverse stressor members, formed of a metal, straddle the fin at regions outside of the channel region and cause, at the regions outside of the channel region, additional transverse stresses in the fin. The magnitude that corresponds to the cut distance, in combination with the additional transverse stresses, induces a longitudinal compressive strain in the channel region.

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract: Devices including stacking faults in sources, or sources and drains, of TFETs are disclosed to improve tunneling efficiency. Embodiments may include a tunneling field-effect transistor comprising a substrate; a source and a drain within the substrate; a gate between the source and the drain; and a stacking fault within the source.

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract: A semiconductor device includes a diffusion area, a gate structure coupled to the diffusion area, and a dummy gate structure coupled to the diffusion area. The gate structure extends a first distance beyond the diffusion area, and the dummy gate structure extends a second distance beyond the diffusion area.

Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.

Abstract: A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions.

Abstract: An isolation region is formed in a semiconductor substrate to laterally define and electrically isolate a device region and first and second laterally adjacent well regions are formed in the device region. A gate structure is formed above the device region such that the first well region extends below an entirety of the gate structure and a well region interface formed between the first and second well regions is laterally offset from a drain-side edge of the gate structure. Source and drain regions are formed in the device region such that the source region extends laterally from a source-side edge of the gate structure and across a first portion of the first well region to a first inner edge of the isolation region and the drain region extends laterally from the drain-side edge and across a second portion of the first well region.

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.