Abstract: A main board and a computer apparatus having the main board are provided. The main board includes a printed circuit board (PCB), a first connector, and a second connector. The PCB is configured for being electrically connected to a processor. The first connector is electrically connected to the PCB in a dual in-line package (DIP) manner, and is configured for a memory to be mounted to the first connector. The second connector is electrically connected to the PCB in a surface mount technology (SMT) manner, and is configured for the memory to be mounted to the second connector. Accordingly, transmission performance of memory signals may be improved.

Abstract: An image-capturing assembly includes a circuit board, an optical filter, an image-capturing element between the circuit board and the optical filter, and a holder. The holder includes a fixing portion. The image-capturing element is on the circuit board and electrically connected to the circuit board. The holder is on an external side of the image-capturing element. The fixing portion has an upper surface and a lower surface opposite to each other, and the lower surface is fixed on the circuit board. The optical filter is fixed on the upper surface of the fixing portion.

Abstract: The present disclosure provides a semiconductor device comprising a substrate; a first III-V compound layer over the substrate; a second III-V compound layer on the first III-V compound layer; a third III-V compound layer on the second III-V compound layer; a source region on the third III-V compound layer; a drain region on the third III-V compound layer; a first dielectric layer arranged on the second III-V compound layer through the third III-V compound layer; and a gate region on the first dielectric layer, wherein a bottom of the gate region is higher than a top surface of the first dielectric layer; the second lateral distance is larger than the first lateral distance.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Abstract: A main board and a computer apparatus having the main board are provided. The main board includes a printed circuit board (PCB), a first connector, and a second connector. The PCB is configured for being electrically connected to a processor. The first connector is electrically connected to the PCB in a dual in-line package (DIP) manner, and is configured for a memory to be mounted to the first connector. The second connector is electrically connected to the PCB in a surface mount technology (SMT) manner, and is configured for the memory to be mounted to the second connector. Accordingly, transmission performance of memory signals may be improved.

Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Abstract: A textile beam management method is disclosed. The textile beam management method includes the following operations: reading the textile beam number of the textile beam; detecting a machine number of a machine; establishing a virtual reader, in which the virtual reader corresponds to the machine; registering the machine number in a report-back list; receiving an event of the machine; and saving the event and/or an ending time of a manufacturing process of the machine in the report-back list.

Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: A support frame adapted for containing a first lens and a second lens, and the support frame includes a body and a first extension bottom wall. The body has a first opening penetrating through the body, a second opening penetrating through the body, a first annular side wall surrounding the first opening, and a second annular side wall surrounding the second opening. The first lens and the second lens are respectively disposed in the first opening and the second opening. The first extension bottom wall integratedly extends from an inner side of the first annular side wall. When the first lens is disposed in the first opening, the first lens is located on the first extension bottom wall. The first extension bottom wall has a first through hole. The first lens corresponds to the first through hole. An image capturing device is further provided.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Abstract: A textile machine adjustment method is provided. An operating speed of a textile machine within an operating range is set by a processor according to the basic information of the fabric. A motion image of the fabric and the vibration characteristics of the yarns are recorded by a video camera. The operating speed of the textile machine is adjusted at least once, and the vibration characteristics of the yarns is analyzed after each adjustment of the operating speed. Multiple correlation factor functions and the relative weights of the multiple factors related to the operating speed of the textile machine are recorded. The relative weights of the multiple factors are adjusted according to a yield quality of the fabric. When an expected value is met, the fabric continues to be produced at the current operating speed; otherwise, the relative weights of multiple factors are adjusted to correct the operating speed.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Abstract: A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.

Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2 DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMI structure and an associated method are also disclosed.

Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.

Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first III-V layer over the substrate, having a first band gap, and a second III-V layer over the first III-V layer, having a second band gap. The second III-V layer includes a first surface in contact with the first III-V layer and a second surface opposite to the first surface. The second band gap at the second surface is greater than the second band gap at the first surface. The present disclosure also provides a manufacturing method of the aforesaid semiconductor structure.