Abstract: A heterostructure may include a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and a deposition layer disposed on the second primary surface of the substrate. The heterostructure may further include an epitaxial layer disposed on the deposition layer.

Abstract: A heterostructure may include a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and a deposition layer disposed on the second primary surface of the substrate. The heterostructure may further include an epitaxial layer disposed on the deposition layer.

Abstract: A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided.

Abstract: A heterostructure including: a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and an epitaxial layer disposed on the second primary surface of the substrate is disclosed along with methods for production of the same.

Abstract: A group III-V transistor device employing a novel layout for isolating and/or defining the active region is provided. A group III-V heterojunction is arranged over or within a substrate, and an inner drain electrode is arranged over the group III-V heterojunction. A gate has a ring shape and is arranged over the group III-V heterojunction around the inner drain electrode. An outer source electrode has a ring-shaped region arranged over the group III-V heterojunction around the gate. A method for manufacturing the group III-V transistor device is also provided.

Abstract: A heterostructure including: a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and an epitaxial layer disposed on the second primary surface of the substrate is disclosed along with methods for production of the same.

Abstract: In a lightweight shoe with a decoration structure and its manufacturing method, the shoe is made of a sole, a body and a decoration ring, and the sole is made of a foaming material, and the colored decoration ring is made of PVC, TPR or TPU and installed between the top rim of the sole and the body and exposed to the exterior for decorating the shoe.

Abstract: A method of eliminating surface roughness of metal lines is disclosed, which can effectively improve the rough edges formed on the surface of the metal lines after wet etching during the manufacturing process of a thin film transistor, so that reliability is increased and current leakage can be avoided. The method includes the steps of: applying a tetra-methyl ammonium hydroxide solution to the rough surface of the metal lines and keeping the metal lines still for a predetermined time; and rinsing the metal lines to remove the tetra-methyl ammonium hydroxide solution left on the surface of the metal lines.