Patents by Inventor Yao-Sheng Lee

Yao-Sheng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11171097
    Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices and bonded to a respective one of the first bonding pads, and at least one metal-organic framework (MOF) dielectric layer that laterally surrounds at least one of the first bonding pads and the second bonding pads.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: November 9, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ramy Nashed Bassely Said, Raghuveer S. Makala, Senaka Kanakamedala, Fei Zhou, Yao-Sheng Lee
  • Publication number: 20210334586
    Abstract: An image processing circuit stores a training database and models in memory. The image processing circuit includes an attribute identification engine to identify an attribute from an input image according to a model stored in the memory. By enhancing the input image based on the identified attribute, a picture quality (PQ) engine in the image processing circuit generates an output image for display. The image processing circuit further includes a data collection module to generate a labeled image based on the input image labeled with the identified attribute, and to add the labeled image to the training database. A training engine in the image processing circuit then re-trains the model using the training database.
    Type: Application
    Filed: March 3, 2021
    Publication date: October 28, 2021
    Inventors: Chih-Wei Chen, Pei-Kuei Tsung, Chia-Da Lee, Yao-Sheng Wang, Hsiao-Chien Chiu, Cheng Lung Jen, Yu-Cheng Tseng, Kuo-Chiang Lo, Yu Chieh Lan
  • Publication number: 20210327889
    Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 21, 2021
    Inventors: Raghuveer S. MAKALA, Senaka KANAKAMEDALA, Fei ZHOU, Yao-Sheng LEE
  • Publication number: 20210327890
    Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 21, 2021
    Inventors: Raghuveer S. MAKALA, Senaka KANAKAMEDALA, Fei ZHOU, Yao-Sheng LEE
  • Publication number: 20210305266
    Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop material layer, and the first-tier alternating stack, and memory opening fill structures each including a memory film and a vertical semiconductor channel located in the inter-tier memory openings. The material of the etch stop material layer is different from materials of the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Inventors: Yao-Sheng Lee, Senaka KANAKAMEDALA, Raghuveer S. Makala, Johann ALSMEIER
  • Publication number: 20210280468
    Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 9, 2021
    Inventors: I-MING CHANG, CHUNG-LIANG CHENG, HSIANG-PI CHANG, HUNG-CHANG SUN, YAO-SHENG HUANG, YU-WEI LU, FANG-WEI LEE, ZIWEI FANG, HUANG-LIN CHAO
  • Patent number: 11114406
    Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 7, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Yao-Sheng Lee, Jian Chen
  • Publication number: 20210265372
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines that are made of molybdenum layers located over a substrate, and memory stack structures extending through each layer in the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Each memory film includes a vertical stack of discrete tubular dielectric metal oxide spacers in contact with a respective one of the molybdenum layers, a continuous silicon oxide blocking dielectric layer contacting an inner sidewall of each of the tubular dielectric metal oxide spacers, a vertical stack of charge storage material portions, and a tunneling dielectric layer contacting each of the charge storage material portions and the vertical semiconductor channel.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 26, 2021
    Inventors: Senaka KANAKAMEDALA, Raghuveer S. MAKALA, Yao-Sheng LEE
  • Publication number: 20210233881
    Abstract: A bonded assembly includes a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices and bonded to a respective one of the first bonding pads, and at least one metal-oxide framework (MOF) dielectric layer that laterally surrounds at least one of the first bonding pads and the second bonding pads.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Ramy Nashed Bassely SAID, Raghuveer S. MAKALA, Senaka KANAKAMEDALA, Fei ZHOU, Yao-Sheng LEE
  • Publication number: 20210193674
    Abstract: A three-dimensional memory device includes a vertically alternating stack of insulating layers and electrically conductive layers located over a top surface of a substrate and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, and each of the insulating layers contains a metal-organic framework (MOF) material portion. The MOF material portion has a low dielectric constant, and reduces RC coupling between the electrically conductive layers. An optional airgap may be located within the MOF material portion to further reduce the effective dielectric constant. Optionally, discrete charge storage regions or floating gates may be formed only at the levels of the electrically conductive layers to reduce program disturb and noise in the device.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Ramy Nashed Bassely SAID, Senaka KANAKAMEDALA, Fei ZHOU, Raghuveer S. MAKALA, Yao-Sheng LEE
  • Publication number: 20210193585
    Abstract: A structure, such as a semiconductor device, includes metal line structures located over a substrate and laterally spaced apart from each other. Each of the metal line structures includes planar metallic liner including a first metal element and a metal line body portion includes a second metal element that is different from the first metal element. Metal-organic framework (MOF) material portions are located between neighboring pairs of the metal line structures and contain metal ions or clusters of the first metal element and organic ligands connected to the metal ions or clusters of the first metal element. Air gaps may be formed in the MOF material portions to further reduce the effective dielectric constant.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Ramy Nashed Bassely SAID, Senaka KANAKAMEDALA, Fei ZHOU, Raghuveer S. MAKALA, Yao-Sheng LEE
  • Patent number: 10950629
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Fei Zhou, Senaka Krishna Kanakamedala, Yao-Sheng Lee
  • Publication number: 20210066347
    Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 4, 2021
    Inventors: Monica Titus, Zhixin Cui, Senaka Kanakamedala, Yao-Sheng Lee, Chih-Yu Lee
  • Patent number: 10847408
    Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Senaka Kanakamedala, Yao-Sheng Lee, Jian Chen
  • Publication number: 20200279868
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Raghuveer S. Makala, Fei Zhou, Senaka Krishna Kanakamedala, Yao-Sheng Lee
  • Patent number: 10741572
    Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: August 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer Makala, Yanli Zhang, Yao-Sheng Lee
  • Publication number: 20200251443
    Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Inventors: Senaka KANAKAMEDALA, Raghuveer S. MAKALA, Yao-Sheng LEE, Jian CHEN
  • Publication number: 20200251374
    Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 6, 2020
    Inventors: Raghuveer S. MAKALA, Senaka KANAKAMEDALA, Yao-Sheng LEE, Jian CHEN
  • Patent number: 10700086
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 30, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Fei Zhou, Senaka Krishna Kanakamedala, Yao-Sheng Lee
  • Patent number: 10622368
    Abstract: Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: April 14, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Somesh Peri, Yao-Sheng Lee, James Kai