Abstract: A vertically alternating sequence of silicon-containing semiconductor layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. After formation of backside trenches, backside recesses are formed by removing the sacrificial material layers employing an isotropic etchant introduced through the backside trenches. Composite electrically conductive layers are formed by reacting a metal layer with surface portions of silicon-containing semiconductor layers. A dielectric material can be anisotropically deposited to form a continuous material portion that includes vertically-extending dielectric material portions formed in the backside trenches and cavity-containing layers formed in the backside recesses. The composite electrically conductive layers include word lines, which are vertically spaced by cavity-containing layers.

Abstract: A phase change memory device includes a vertical stack of multiple two-dimensional arrays of pillar structures. Each of the multiple two-dimensional arrays of pillar structures is located within a respective array level. Each two-dimensional array among the multiple two-dimensional arrays of pillar structures is contacted by a respective overlying one-dimensional array of conductive rails laterally extending along a first horizontal direction and a respective underlying one-dimensional array of conductive rails laterally extending along a second horizontal direction different from the first direction. Each pillar structure within the multiple two-dimensional arrays of pillar structures includes a phase change memory element and a selector element in a series connection with the phase change memory element. A first set of dielectric isolation structures having a first homogeneous composition vertically extends continuously through two vertically neighboring array levels.

Abstract: A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.

Abstract: A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.

Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at leas

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at leas

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

Abstract: A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical contact with the boron doped semiconductor active regions, the device contact via structures containing at least one of tantalum, tungsten, and cobalt, and a three-dimensional memory array located over the driver transistors and including an alternating stack of insulating layers and electrically conductive layers and memory structures vertically extending through the alternating stack.

Abstract: Memory openings and support openings can be formed through an alternating stack of insulating layers and sacrificial material layers. A set of dielectric layers and at least one semiconductor material layer can be sequentially deposited in each of the memory openings and the support openings. The at least one semiconductor material layer is removed from inside the support openings, while the at least one semiconductor material layer is not removed from inside the memory openings. Memory stack structures and support pillar structures are formed in the memory openings and the support openings, respectively. The sacrificial material layers are replaced with electrically conductive layers. Removal of the at least one semiconductor material layer from the support pillar structures reduces or eliminates leakage current through the support pillar structures.

Abstract: After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.

Abstract: Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.

Abstract: After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.

Abstract: A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, a memory opening extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film, and a dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.

Abstract: A three-dimensional non-volatile memory comprises a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate. Higher word lines are implemented to be thicker than lower word lines in order to reduce variation in resistance among word lines.

Abstract: A memory stack structure including a memory film and a vertical semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulating layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulating layers, a backside blocking dielectric layer may be formed in the backside recesses and sidewalls of the memory stack structures. A metallic barrier material portion can be formed in each backside recess. A metallic material portion is formed on the metallic barrier material portion. Subsequently, a metal portion comprising a material selected from cobalt and ruthenium is formed directly on a sidewall of the metallic barrier material portion and a sidewall of the metallic material portion and an overlying insulating surface and an underlying insulating surface.

Abstract: A sacrificial film and an alternating stack of insulating layers and sacrificial material layers are sequentially formed over a substrate. A memory stack structure including a memory film and a vertical semiconductor channel is formed through the alternating stack and the sacrificial film on the substrate. A source level cavity is formed by introducing an etchant or a reactant through a backside trench and removing the sacrificial film. After removal of an annular portion of the memory film, a portion of the vertical semiconductor channel is converted into an annular source region by introducing electrical dopants into the channel. A source contact layer is formed in the source level cavity and directly on the annular source region. The sacrificial material layers are replaced with electrically conductive layers. The annular source region and the source contact layer can provide low source contact resistance in a three-dimensional NAND memory device.

Abstract: A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during formation of a three-dimensional memory device. The silicon-containing nucleation layer may remain as a silicon layer, converted into a tungsten silicide layer, or replaced with a tungsten nucleation layer. Tungsten deposition can proceed only on the surface of the silicon-containing nucleation layer or a layer derived therefrom in a subsequent tungsten deposition process.

Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.