Abstract: Provided are an integrated circuit chip apparatus and a related product, the integrated circuit chip apparatus being used for executing a multiplication operation, a convolution operation or a training operation of a neural network. The present technical solution has the advantages of a small amount of calculation and low power consumption.

Abstract: An optoelectronic device includes a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a first insulating layer on the second semiconductor layer and including a plurality of first openings exposing the first semiconductor layer, wherein the first openings include a first group and a second group; a third electrode on the first insulating layer and including a first extended portion and a second extended portion, wherein the first extended portion and the second extended portion are respectively electrically connected to the first semiconductor layer through the first group of the first openings and the second group of the first openings, and wherein the number of the first group of the first openings is different from the number of the second group of the first openings; and a plurality of fourth electrodes on the second insulating layer and electrically connected to the second semiconductor layer, wherein in a

Abstract: A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.

Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.

Abstract: A 3D stacked packaging structure and a manufacturing method thereof are provided. The 3D stacked packaging structure includes a bottom-layer structure and a top-layer structure stacked thereon. The bottom-layer structure and the top-layer structure each include: a substrate layer; a diamond layer grown on the substrate layer; an ion-implanted silicon wafer layer attached to the diamond layer; and a component layer provided on the silicon wafer layer, with the four layers stacked together in sequence, wherein the substrate layer of the top-layer structure is in contact with the component layer of the bottom-layer structure, and at least one through hole provided between the bottom-layer structure and the top-layer structure, extends through the component layer, the ion-implanted silicon wafer layer, the diamond layer, and the substrate layer of the top-layer structure, and extends through the component layer of the bottom-layer structure, and is filled with a conductive material.

Abstract: This disclosure provides various techniques for providing fine-grain digital and analog pixel compensation to account for voltage error across an electronic display. By employing a two-dimensional digital compensation and a local analog compensation, a fine-grain and robust pixel compensation scheme may be provided to the electronic display.

Abstract: A method manufacturing of a semiconductor structure including following steps is provided. A material layer is provided. A first mask layer is formed on the material layer. Core patterns are formed on the first mask layer. A spacer material layer is conformally formed on the core patterns. An etch-back process is performed on the spacer material layer. A portion of the spacer material layer located on two ends of the core pattern is removed, then spacer structures are formed. Each spacer structure includes a merged spacer and a non-merged spacer. The core patterns are removed. The first patterned mask layer is formed to cover a portion of the merged spacer and expose another portion of the merged spacer and the non-merged spacer. The first patterned mask layer and the spacer structure are used as a mask, and the first mask layer is patterned into a second patterned mask layer.

Abstract: A liquid crystal display panel is provided. The liquid crystal display panel includes: a first substrate and a second substrate arranged opposite to each other, and a liquid crystal layer and a plurality of strip-shaped spacers disposed between the first substrate and the second substrate. In the liquid crystal display panel, there is an overlapping area between an orthographic projection of a first signal line on a target base and an orthographic projection of a second signal line on the target base, and an orthographic projection of the strip-shaped spacer on the target base is not overlapped with the overlapping area.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

Abstract: Provided herein is a potassium-binding polymer prepared by polymerization reaction of a monomer and a crosslinking agent, wherein the monomer is the compound of formula (V), the crosslinking agent is the compound of formula (VI), and/or the compound of formula (VII), wherein the variables are as defined in the specification; to the use thereof for treating or preventing hyperkalemia.

Abstract: An array substrate, an opposite substrate and a display panel are provided. The array substrate comprises: a display region and a periphery region surrounding the display region, wherein the display region comprises a plurality of pixel regions, and each of the pixel regions comprises a reflective region and a transmissive region; the reflective region comprises a driving signal outputting layer, a segment gap layer, a passivation layer and a reflective layer, the reflective layer is coupled to the driving signal outputting layer to enable both the reflective layer and the driving signal outputting layer to function as a reflective region driving electrode; the transmissive region comprises a first electrode layer, the first electrode layer is coupled to the driving signal outputting layer, the passivation layer extends to the transmissive region, and the passivation layer is arranged between the first electrode layer and a first base of the display substrate.

Abstract: A display substrate and a display apparatus. The display substrate includes sub-pixels. An orthographic projection of a first anode structure overlaps that of a first pixel driving circuit to form a first overlapping region. An orthographic projection of a second anode structure overlaps that of a second pixel driving circuit to form a second overlapping region. An area of the first overlapping region is less than that of the second overlapping region. The orthographic projection of the first anode structure overlaps that of a driving gate conductive portion of the first pixel driving circuit to form a third overlapping region. The orthographic projection of the second anode structure overlaps that of a driving gate conductive portion of the second pixel driving circuit to form a fourth overlapping region. A ratio of an area of the third overlapping region to that of the fourth overlapping region ranges from 0.8 to 1.2.

Abstract: The present disclosure belongs to the technical field of wastewater treatment, and discloses an electrochemical nitrogen and phosphorus removal device and a method.

Abstract: An array substrate includes a first substrate; and a first electrode and a second electrode disposed on the first substrate and located in a sub-pixel region. At least one of the first electrode and the second electrode includes a plurality of electrode strips. Every two adjacent electrode strips in the first electrode and the second electrode have a slit therebetween. The slit includes a first end portion, a straight portion, and a second end portion connected in sequence. A bend is formed at a connection position of the first end portion and the straight portion, and the second end portion is formed by protruding from the straight portion. The straight portion includes a first edge and a second edge parallel to each other, and an average width of the first end portion in a direction perpendicular to the first edge is less than a width of the straight portion.

Abstract: A pixel circuit and a driving method thereof, a display substrate and a display device are provided. The pixel circuit includes a driving sub-circuit, a first switch sub-circuit and a first light-emitting control sub-circuit. The driving sub-circuit includes a control terminal connected with a first node, a first terminal connected with a second node and a second terminal connected with a third node, and is configured to control a driving signal from the first node to the third node for driving a light-emitting element; the first switch sub-circuit is configured to control conduction of the driving signal between the third node and a fourth node; the first light-emitting control sub-circuit is connected with a first electrode of the light-emitting element through a fifth node, and is configured to control conduction of the driving signal between the fourth node and the fifth node.

Abstract: A method and system for identifying bonding between a material and tubing. The method may include disposing an acoustic logging tool in a wellbore, wherein the acoustic logging tool comprises a transmitter, a receiver, or a transceiver, broadcasting a shaped signal with the transmitter such that the shaped signal interacts with a boundary of a casing and a material and recording a result signal from the boundary with the receiver. The method may further comprise identifying a cut-off time to be applied to the result signal, transforming the result signal from a time domain to a frequency domain, selecting one or more modes sensitive to a bonding at the boundary between the casing and the material, computing a decay rate of the one or more modes that were selected based at least one or more decay curves, and converting the decay rate to a bonding log.

Abstract: A filament forming method includes: performing first stage to apply first bias including gate and drain voltages to a resistive memory unit plural times until read current reaches first saturating state, latching read current in first saturating state as saturating read current, determining whether rate of increase of saturating read current is less than first threshold value; when rate of increase of saturating read current is not less than first threshold value, performing second stage to apply second bias, by increasing gate voltage and decreasing drain voltage, to the resistive memory unit plural times until read current reaches second saturating state, latching read current in second saturating state as saturating read current and determining whether rate of increase of saturating read current is less than first threshold value; finishing the method when rate of increase of saturating read current is less than first threshold value and saturating read current reaches target current value.

Abstract: Machine learning is used to train a network to estimate a three-dimensional (3D) body surface and body regions of a patient from surface images of the patient. The estimated 3D body surface of the patient is used to determine an isocenter of the patient. The estimated body regions are used to generate heatmaps representing visible body region boundaries and unseen body region boundaries of the patient. The estimation of 3D body surfaces, the determined patient isocenter, and the estimated body region boundaries may assist in planning a medical scan, including automatic patient positioning.

Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, being not overlapped but being spaced apart. The third sub-pixel includes a first edge facing the first sub-pixel, the first sub-pixel includes a second edge facing the third sub-pixel, the third sub-pixel includes a third edge facing the second sub-pixel, and the second sub-pixel includes a fourth edge facing the third sub-pixel, and shapes of the first sub-pixel and the second sub-pixel are circles, the first edge and the second edge are curved edges with a same curvature, the third edge and the fourth edge are curved edges with a same curvature; or shapes of the first sub-pixel and the second sub-pixel are octagons, at least part of the first edge is parallel to at least part of the second edge, at least part of the third edge is parallel to at least part of the fourth edge.

Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.