Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.

Abstract: A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.

Abstract: The present invention provides a smart wearable IOT device configured to be worn by a subject on the body and is capable of continuously tracking and reporting a plurality of vital signs and physical activities of the user, including but not limited to sound and vibrational dynamics due to breathing and coughing (from which we can derive the breathing and coughing types and features), body temperature, peripheral oxygen saturation (SpO2), heart rate, and fatigue-related mobility, physical ability, step count, photoplethysmogram (PPG), ECG, heart rate, heart rate variability, etc. In one aspect, the wearable system will be able to measure the distance with different users through the transmit and receive of Bluetooth low energy signals or WiFi to trace contacts between different wearers. The system will be able to record the data locally on a SD card and also will be able to upload on a server.

Abstract: An exercise intensity assessing system includes a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser exercises. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database for being diagnosed and analyzed by a fitness instructor. The cloud database obtains a forecasted watt value corresponding to the physiological information, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.

Abstract: Cement bonding evaluation and logging in a wellbore environment are described. The cement bonding evaluation is performed using data associated with and processed from the measurement of sonic waves directed to and dissipated by the casing present in the wellbore.

Abstract: An intelligent exercise intensity assessing system includes an exercise testing machine, a physiological information sensor, a signal transmitter connected with the physiological information sensor, a central control host connected with the signal transmitter, and a cloud database connected with the central control host. The physiological information sensor senses physiological information of an exerciser before and after the exerciser operates the exercise testing machine. The physiological information is transmitted by the signal transmitter to the central control host, and transmitted by the central control host to the cloud database. The cloud database analyzes the physiological information to obtain a corresponding forecasted watt value, and obtains a resistance level of different fitness apparatuses according to the forecasted watt value.

Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.

Abstract: Machine learning model training is provided. A model training result of a machine learning model is predicted utilizing a classification model based on a plurality of different combinations of input data set properties, settings of the machine learning model, and machine learning model training environment properties. Model training duration of the machine learning model is predicted utilizing a regression model based on those combinations that had a predicted successful model training result. Capacity unit hours is determined for each respective combination having the predicted successful model training result based on a corresponding predicted model training duration of the machine learning model. A particular combination of input data set properties, settings of the machine learning model, and machine learning model training environment properties that has minimum capacity unit hours is selected. The machine learning model is trained using the particular combination.

Abstract: A vehicle tire cloud computing management system and an application method thereof are provided. A vehicle tire cloud computing management system is formed by combining a vehicle tire management device including tire sensors, a setting tool, and radio frequency identification (RFID) tags with a cloud server, and a car computer. By using the tire sensors to detect tire-related data, and then by outputting the tire-related data to the setting tool, the cloud server, or the car computer for data computation, result judging and/or data storage, so that the function of the tire sensors is more focused on detecting tire conditions, and power consumption of the tire sensors is reduced, while the setting tool, the cloud server, and the car computer are used efficiently to perform computation, management, and application for data related to the tire sensors.

Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.

Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: The present invention belongs to the pharmaceutical field, and relates to an application of a cilostazol and d-borneol composition in preparing a drug for treating cerebrovascular disease, in particular ischemic cerebrovascular disease. The present invention specifically relates to a composition containing cilostazol or a pharmaceutically acceptable salt thereof and d-borneol, and an application of the composition in preparing a drug for treating cerebrovascular disease, in particular ischemic cerebrovascular disease.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. A conductive upper electrode is arranged over the magnetic tunnel junction. Below the conductive lower electrode is a first conductive via structure in a first dielectric layer. Below the conductive via structure is a discrete conductive jumper structure in a second dielectric layer. A dielectric body of a third dielectric material that is different from the first dielectric material and the second dielectric material extends vertical from the first dielectric layer at least partially into the second dielectric layer.

Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.

Abstract: A display substrate and a display panel are provided.

Abstract: A display substrate. In a plane parallel to the display substrate, the display substrate includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit, the pixel driving circuit at least includes a storage capacitor and a plurality of transistors, the plurality of transistors at least includes a driving transistor and at least one switching transistor of a dual-gate structure. In a plane perpendicular to the display substrate, the display substrate includes a plurality of conductive layers, the first polar plate and the gate electrode of the drive transistor are arranged in the same layer, the second polar plate and the first power line are arranged in the same layer.

Abstract: A display panel, includes: a substrate; and a plurality of OLED devices disposed on the substrate, each of which includes an anode and a light-emitting layer arranged in stack; further includes a patterned area, the patterned area comprising at least one cathode group, each of which includes a plurality of cathodes arranged at intervals, and an orthographic projection of each of the plurality of cathodes on the substrate at least covers an orthographic projection of the light-emitting layer of one of the plurality of OLED devices on the substrate; and for each of the at least one cathode group, the display panel further includes a plurality of first wirings electrically connected to the plurality of cathodes in one-to-one correspondence and a second wiring electrically connected to the plurality of first wirings and electrically connected to a VSS signal line. A display device is further provided.

Abstract: A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has an U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

Abstract: A splicing component and a spliced display screen are provided. In the splicing component provided by the embodiments of the present disclosure, splicing panels are aligned and preliminarily spliced through a first positioning structure and a second positioning structure. A first splicing part and a second splicing part are then connected through a connecting part. Therefore, a plurality of splicing panels are efficiently and seamlessly spliced through the splicing component. The splicing component provided by the embodiment of the present disclosure improves the mounting efficiency of a spliced display screen and simplifies the mounting mode.