Patents by Inventor Yaping Zhou

Yaping Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240400966
    Abstract: An automatic disinfection machine for plant tissue culture explants, comprising a water tank, a disinfection basket, solution bottles, pumps and a valve, wherein the solution bottles are arranged in multiple and respectively filled with disinfectants and sterile water, on the water tank are provided a water inlet and a water outlet, the disinfection basket is detachably placed inside the water tank to hold plant tissues, each of the solution bottles is connected to the water inlet through one of the pumps, and the valve is provided at the water outlet and is opened at a specified time after the pumps are started. In the present invention, a controller is arranged to open the pumps and the valve, so to infuse disinfectants or sterile water into the water tank, as well as automatically discharge disinfectants or sterile water from the water tank, thereby performing disinfection and rinsing automatically without manual operation.
    Type: Application
    Filed: September 20, 2023
    Publication date: December 5, 2024
    Inventors: Xiao ZHENG, Yaping HU, Xiaomin GE, Hui DING, Shuifei CHEN, Xu ZHOU
  • Publication number: 20240383817
    Abstract: Disclosed are an integrated method and an integrated system for resource recovery of source-separated urine. The integrated method for resource recovery of the source-separated urine includes: mixing the source-separated urine with an alkali metal peroxysulphate to obtain a mixture, and subjecting the mixture to evaporation-concentration by heating to obtain condensed water and a liquid compound fertilizer, where the liquid compound fertilizer includes urea, a phosphorus salt, and a potassium salt.
    Type: Application
    Filed: November 8, 2023
    Publication date: November 21, 2024
    Inventors: Zifu LI, Yaping LYU, Xuemei WANG, Xiaoqin ZHOU, Rui FENG, Xiuwei AO, Shikun CHENG
  • Patent number: 12111080
    Abstract: The invention provides a heat-storage medium conveying system for a solar-thermal power plant. The system includes a high-level tank subsystem including a high-level tank used to store the heat-storage medium. The system further includes a heat-storage medium transport subsystem. The high-level tank subsystem is connected with the heat-storage medium transport subsystem. The heat-storage medium transport subsystem includes a low-level tank. A mounting height of the low-level tank is lower than that of the high-level tank. A volume of the low-level tank is smaller than a volume of the high-level tank. The heat-storage medium can enter the low-level tank from the high-level tank partially or completely by its own gravity. The low-level tank is provided with a conveying pump, and the heat-storage medium is pumped out of the low-level tank through the conveying pump.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 8, 2024
    Assignee: Zhejiang Cosin Solar Technology Co., Ltd.
    Inventors: Zhiyong Yu, Yaping Tang, Hui Zhou, Kai Zhou, Wenjian Bi, Feng Sun, Juan Tang, Guokai Tong
  • Publication number: 20240292355
    Abstract: This disclosure provides a method of dynamically adjusting timing between adjacent networks in a synchronous network and an electronic shelf label system. The method includes: determining, by a server, a timing adjustment direction and a timing adjustment value of a current network based on an interference timing relationship diagram; generating, by the server, a corresponding adjustment task form the timing adjustment direction and the timing adjustment value of the current network, and sending the adjustment task to a master base station in the current network in the processing of each of the current networks, such that the master base station and a secondary base station dynamically adjust timing based on the adjustment task.
    Type: Application
    Filed: April 8, 2024
    Publication date: August 29, 2024
    Applicant: HANSHOW TECHNOLOGY CO., LTD.
    Inventors: Yaping JI, Xi ZHONG, Guofeng ZHANG, Qi JIANG, Jun ZHOU, Min LIANG
  • Publication number: 20230102044
    Abstract: This present disclosure provides a bulk acoustic wave resonator and a bulk acoustic wave filter, and relates to the technical field of filters. A substrate and a piezoelectric stack structure arranged on the substrate are included. The piezoelectric stack structure includes a bottom electrode, a piezoelectric material layer and a top electrode which are sequentially stacked, and an outline of an orthographic projection of the top electrode on the substrate includes at least one Bezier curve of order greater than or equal to 2.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 30, 2023
    Inventors: Bowoon SOON, Yao CAI, Jian WANG, Kunli ZHAO, Junwu ZHAO, Yaping ZHOU, Chao GAO, Chengliang SUN
  • Patent number: 11600554
    Abstract: A device including a stack of dies. Each of the dies can have unit stair-step conductive paths of connection features which include through-die via structures and routing structures. The unit stair-step conductive paths of one of the dies can be interconnected to another one of the unit stair-step conductive paths of another one of the dies to form one of a plurality conductive stair-case structures through two or more of the dies. The unit stair-step conductive paths can be connected to reduce signal cross talk between the conductive stair-case structures whereby at least some of the conductive stair-case structures are connected to transmit a same polarity of electrical signals are spatially separated in a dimension that is perpendicular to a major surface of the dies. A method of manufacturing the device is also disclosed.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: March 7, 2023
    Assignee: NVIDIA Corporation
    Inventors: Walker J. Turner, Yaping Zhou, John M. Wilson
  • Publication number: 20230034619
    Abstract: A device including a stack of dies. Each of the dies can have unit stair-step conductive paths of connection features which include through-die via structures and routing structures. The unit stair-step conductive paths of one of the dies can be interconnected to another one of the unit stair-step conductive paths of another one of the dies to form one of a plurality conductive stair-case structures through two or more of the dies. The unit stair-step conductive paths can be connected to reduce signal cross talk between the conductive stair-case structures whereby at least some of the conductive stair-case structures are connected to transmit a same polarity of electrical signals are spatially separated in a dimension that is perpendicular to a major surface of the dies. A method of manufacturing the device is also disclosed.
    Type: Application
    Filed: August 2, 2021
    Publication date: February 2, 2023
    Inventors: Walker J. Turner, Yaping Zhou, John M. Wilson
  • Patent number: 10685925
    Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 16, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Patent number: 10600730
    Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: March 24, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Publication number: 20190237417
    Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Publication number: 20190237399
    Abstract: In one embodiment, a system comprises: a plurality of aggressor bus lines; and a plurality of differential pair bus lines that are located in relatively parallel close proximity to the plurality of aggressor bus lines, wherein at least two of the plurality of differential pair bus lines change location with respect to each other at a point that has a cancelling affect on cross talk from the plurality of aggressor bus lines, wherein the change includes cross over routing. The plurality of differential pair bus lines can convey differential clock signals. The routing of the plurality of differential pair bus lines is substantially parallel to one another before and after the change.
    Type: Application
    Filed: January 26, 2018
    Publication date: August 1, 2019
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Patent number: 9843511
    Abstract: The embodiments disclose a method and apparatus of selecting a path for transmission from paths between a first LER and a second LER in the MPLS network. The method may comprise: obtaining state information of the paths between the first LER and the second LER, the state information may indicate that a path is in up state or down state; obtaining stability information of at least one of the paths between the first LER and the second LER, the stability information may indicate that a path is stable or unstable; and selecting a path for transmission based on the state information and the stability information.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: December 12, 2017
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Yaping Zhou, Cuihua Deng
  • Patent number: 9831198
    Abstract: An active component of an integrated voltage regulator (IVR) circuit is deployed within an IC device for regulating an operating voltage thereof. An interposer interconnects the IC device with a power source. A passive inductive component of the IVR circuit is deployed upon a surface of the IC device or the interposer. The inductive component has a magnetic core and a winding (e.g., wire-bond), wound about the magnetic core.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: November 28, 2017
    Assignee: Nvidia Corporation
    Inventors: Yaping Zhou, Huabo Chen, Wenjie Mao
  • Publication number: 20160173372
    Abstract: The embodiments disclose a method and apparatus of selecting a path for transmission from paths between a first LER and a second LER in the MPLS network. The method may comprise: obtaining state information of the paths between the first LER and the second LER, the state information may indicate that a path is in up state or down state; obtaining stability information of at least one of the paths between the first LER and the second LER, the stability information may indicate that a path is stable or unstable; and selecting a path for transmission based on the state information and the stability information.
    Type: Application
    Filed: July 31, 2013
    Publication date: June 16, 2016
    Inventors: Yaping Zhou, Cuihua Deng
  • Patent number: 9306776
    Abstract: A method for filtering a data signal includes transmitting the data signal from a transmitter to a receiver across a conductor disposed in an interposer, which interconnects the receiver and the transmitter. The data signal is low-passed with a filter, which includes a passive resistive element disposed within the interposer and coupled in series electrically with a passive inductive element. In relation thereto, the interposer is disposed in a position within the interposer, or upon a surface thereof. The filter is coupled to the conductor in a shunt configuration with respect to ground.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: April 5, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Yaping Zhou, Wenjie Mao, Huabo Chen, Mayan Riat
  • Publication number: 20160072640
    Abstract: Embodiments of the present invention provide a method and system for reducing congestion on a communication network. The communication network includes a network node having a first port and a second port. The network node is associated with forwarding data including first port forwarding data identifying at least one node accessible via the first port, and second port forwarding data identifying at least one node accessible via the second port. A failure associated with one of the first port and the second port is determined. The forwarding data corresponding to the other of the first port and the second port not associated with the failure, is updated with the one of the first port forwarding data and second port forwarding data corresponding to the one of the first port and the second port associated with the failure.
    Type: Application
    Filed: March 29, 2012
    Publication date: March 10, 2016
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Juan Yang, Yaping Zhou, Ke Lin
  • Patent number: 9270476
    Abstract: The present disclosure relates to a network protection scheme. In one embodiment, there provides a method for network protection, including the steps of: detecting a switch indicator in a network; setting a rate limit of storm protection, which is of a first value, as a second value, the second value being higher than the first value; and performing a flush operation of a Forwarding DataBase FDB.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: February 23, 2016
    Assignee: TELEFONAKTIEBOLAGET L M ERICSSON
    Inventors: Yaping Zhou, Junhui Liu
  • Publication number: 20150071333
    Abstract: A method for filtering a data signal includes transmitting the data signal from a transmitter to a receiver across a conductor disposed in an interposer, which interconnects the receiver and the transmitter. The data signal is low-passed with a filter, which includes a passive resistive element disposed within the interposer and coupled in series electrically with a passive inductive element. In relation thereto, the interposer is disposed in a position within the interposer, or upon a surface thereof. The filter is coupled to the conductor in a shunt configuration with respect to ground.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Applicant: Nvidia Corporation
    Inventors: Yaping Zhou, Wenjie Mao, Huabo Chen, Mayan Riat
  • Publication number: 20150054573
    Abstract: An active component of an integrated voltage regulator (IVR) circuit is deployed within an IC device for regulating an operating voltage thereof. An interposer interconnects the IC device with a power source. A passive inductive component of the IVR circuit is deployed upon a surface of the IC device or the interposer. The inductive component has a magnetic core and a winding (e.g., wire-bond), wound about the magnetic core.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: Nvidia Corporation
    Inventors: Yaping Zhou, Huabo Chen, Wenjie Mao
  • Publication number: 20140328160
    Abstract: The present disclosure relates to a network protection scheme. In one embodiment, there provides a method for network protection, including the steps of: detecting a switch indicator in a network; setting a rate limit of storm protection, which is of a first value, as a second value, the second value being higher than the first value; and performing a flush operation of a Forwarding DataBase FDB.
    Type: Application
    Filed: January 17, 2012
    Publication date: November 6, 2014
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Yaping Zhou, Junhui Liu