Patents by Inventor Yaping Zhou

Yaping Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060065966
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Application
    Filed: November 9, 2005
    Publication date: March 30, 2006
    Inventors: Yaping Zhou, Chu-Chung Lee
  • Patent number: 6998952
    Abstract: An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends between the core (109) and the substrate (225). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (117, 116). The second plurality of bond wires (111) extends over the core (109) and is coupled between two of the plurality of wire bond pads (117, 119). A shield (141) includes a portion that is positioned between the core (109) and the substrate (225).
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: February 14, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaping Zhou, Susan H. Downey, Sheila F. Chopin, Tu-Anh Tran, Alan H. Woosley, Peter R. Harper, Perry H. Pelley, III
  • Patent number: 6992377
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: January 31, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaping Zhou, Chu-Chung Lee
  • Publication number: 20050189643
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 1, 2005
    Inventors: Yaping Zhou, Chu-Chung Lee
  • Patent number: 6933599
    Abstract: A semiconductor device has a die (10) overlying and electrically connected to a support structure (11), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects (32, 38) are noise sources to victim interconnects (29, 59) carrying sensitive signals. An arrangement of shield interconnects (51-58) surround the victim interconnect (29, 59) in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: August 23, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bennett A. Joiner, Yaping Zhou, Ben W. Herberg
  • Publication number: 20050122198
    Abstract: An inductive device (105) is formed above a substrate (225) having a conductive coil formed around a core (109). The coil comprises segments formed from a first plurality of bond wires (113) and a second plurality of bond wires (111). The first plurality of bond wires (113) extends between the core (109) and the substrate (225). Each of the first plurality of bond wires is coupled to two of a plurality of wire bond pads (117, 116). The second plurality of bond wires (111) extends over the core (109) and is coupled between two of the plurality of wire bond pads (117, 119). A shield (141) includes a portion that is positioned between the core (109) and the substrate (225).
    Type: Application
    Filed: December 5, 2003
    Publication date: June 9, 2005
    Inventors: Yaping Zhou, Susan Downey, Sheila Chopin, Tu-Anh Tran, Alan Woosley, Peter Harper, Perry Pelley
  • Publication number: 20050087856
    Abstract: A semiconductor device has a die (10) overlying and electrically connected to a support structure (11), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects (32, 38) are noise sources to victim interconnects (29, 59) carrying sensitive signals. An arrangement of shield interconnects (51-58) surround the victim interconnect (29, 59) in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.
    Type: Application
    Filed: October 27, 2003
    Publication date: April 28, 2005
    Inventors: Bennett Joiner, Yaping Zhou, Ben Herberg