Patents by Inventor Yaping Zhou

Yaping Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130075148
    Abstract: A device and/or apparatus having plated through holes (PTHs) which are coated to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
    Type: Application
    Filed: March 22, 2012
    Publication date: March 28, 2013
    Applicant: IBM CORPORATION
    Inventors: Paul M. Harvey, Douglas O. Powell, Wolfgang Sauter, Yaping Zhou
  • Patent number: 8399981
    Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Roger D. Weekly, Yaping Zhou
  • Publication number: 20130015573
    Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 17, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yaping Zhou, Roger D. Weekly
  • Patent number: 8338949
    Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
  • Patent number: 8338948
    Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Roger D. Weekly, Yaping Zhou
  • Patent number: 8222739
    Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
    Type: Grant
    Filed: December 19, 2009
    Date of Patent: July 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
  • Publication number: 20120175763
    Abstract: An integrated circuit package includes a package core and a primary circuitry chip mounted on the package core. The primary circuitry chip has an active surface in which the core circuitry is fabricated. The active surface of the primary circuitry chip faces the package core and includes contacts. The integrated circuit package further includes an auxiliary circuit chip assembled to the package core and having contacts facing and electrically connected to the contacts of the primary circuitry chip.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: PAUL M. HARVEY, ROHAN U. MANDREKAR, SAMUEL W. YANG, YAPING ZHOU
  • Publication number: 20120138349
    Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
    Type: Application
    Filed: February 8, 2012
    Publication date: June 7, 2012
    Applicant: International Business Machines Corporation
    Inventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
  • Patent number: 8193800
    Abstract: A method and system for reducing the noise level of a power supply system with the implementation of a voltage controlled decoupling capacitor in an electrical circuit. Voltage variations of the power supply caused by switching currents are detected by a voltage sensor control circuit. The voltage sensor circuit compares a stable reference voltage with the varying voltage level of the power supply in order to generate a sensor control voltage. When applied to the decoupling capacitor, the control voltage adjusts the capacitance of the voltage controlled capacitor. The adjusted capacitance allows the voltage controlled decoupling capacitor to compensate for the effects of the voltage variations by supplying an increased quantity of charge to various circuit components. Thus, the voltage controlled capacitor is able to efficiently reduce noise within the power supply system.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventor: Yaping Zhou
  • Publication number: 20120001327
    Abstract: An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns.
    Type: Application
    Filed: June 30, 2010
    Publication date: January 5, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yaping Zhou, Roger D. Weekly
  • Publication number: 20110147044
    Abstract: A system to improve core package connections may include ball grid array pads, and a ball grid array. The system may also include connection members of the ball grid array conductively connected to respective ball grid array pads. The system may further include magnetic underfill positioned adjacent at least some of the connection members and respective ball grid array pads to increase respective connection members' inductance.
    Type: Application
    Filed: December 19, 2009
    Publication date: June 23, 2011
    Applicant: International Business Machines Corporation
    Inventors: Paul M. Harvey, Colm B. O'Reilly, Samuel W. Yang, Yaping Zhou
  • Publication number: 20100017158
    Abstract: A methodology to determine a bit pattern that may excite a worse case or near worse case simultaneous switching noise on a memory or input/output (IO) interface of a digital system is provided. This methodology involves determining an impedance profile of the IO interface of the digital system. The amplitude response of signal X(f) may be matched in the impedance profile of the IO interface. The phase response of the signal X(f) is also set. The signal X(f) having a matched amplitude response may be converted from a frequency domain signal to a time domain signal to produce a signal X(t). Signal X(t) the time domain signal X(t) may be digitized to represent a bit stream B(t).
    Type: Application
    Filed: July 21, 2008
    Publication date: January 21, 2010
    Inventors: Rohan Mandrekar, Paul Marlan Harvey, Yaping Zhou, Kazushige Kawasaki
  • Publication number: 20090302874
    Abstract: A method and apparatus for probing a circuit board, is provided. One implementation involves a signal probe including a tip having a plurality of strands of flexible conductive material surrounding the tip, the strands extending out from the tip to provide multiple points of contact with the rim of a via or a conductive barrel of the via when the tip is inserted into the via, the probe tip and probe strands being made of same conductive material; such that aligning the signal probe with the via for engaging the probe tip strands with the via, and inserting the tip into the via, causes bending and flexing of the strands for making contact with a conductor on a top rim of the barrel and inside an inner wall of the barrel.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Applicant: International Business Machines Corporation
    Inventors: Paul M. Harvey, Samuel W. Yang, Yaping Zhou
  • Publication number: 20090189713
    Abstract: A method and system for reducing the noise level of a power supply system with the implementation of a voltage controlled decoupling capacitor in an electrical circuit. Voltage variations of the power supply caused by switching currents are detected by a voltage sensor control circuit. The voltage sensor circuit compares a stable reference voltage with the varying voltage level of the power supply in order to generate a sensor control voltage. When applied to the decoupling capacitor, the control voltage adjusts the capacitance of the voltage controlled capacitor. The adjusted capacitance allows the voltage controlled decoupling capacitor to compensate for the effects of the voltage variations by supplying an increased quantity of charge to various circuit components. Thus, the voltage controlled capacitor is able to efficiently reduce noise within the power supply system.
    Type: Application
    Filed: January 28, 2008
    Publication date: July 30, 2009
    Inventor: Yaping Zhou
  • Publication number: 20090126983
    Abstract: A method, system and apparatus for coating plated through holes (PTHs) to reduce impedance discontinuity in electronic packages. PTH vias are imbedded in the core of a printed circuit board comprising a core layer, a plurality of buildup layers, a plurality of micro-vias, and a plurality of traces. Traces electrically interconnect each of the micro-vias to PTH vias, forming an electrically conductive path. PTHs are coated with a magnetic metal material, such as nickel, to increase the internal and external conductance of the PTHs, thereby providing decreased impedance discontinuity of the signals in electronic packages.
    Type: Application
    Filed: November 19, 2007
    Publication date: May 21, 2009
    Inventors: Paul M. Harvey, Douglas O. Powell, Wolfgang Sauter, Yaping Zhou
  • Publication number: 20080189090
    Abstract: A system and method for determining a guard band for an operating voltage of an integrated circuit device are provided. The system and method provide a mechanism for calculating the guard band based on a comparison of simulated noise obtained from a simulation of the integrated circuit device using a worst case waveform stimuli with simulated or measured power supply noise of a workload/test pattern that may be achieved using testing equipment. A scaling factor for the guard band is determined by comparing results of a simulation of a workload/test pattern with measured results of the workload/test pattern as applied to a hardware implementation of the integrated circuit device. This scaling factor is applied to a difference between the noise generated through simulation of the workload/test pattern and the noise generated through simulation of the worst case current waveform to generate a guard band value.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Inventors: Makoto Aikawa, Sang H. Dhong, Brian Flachs, Gilles Gervais, Yoichi Nishino, Iwao Takiguchi, Tetsuji Tamura, Yaping Zhou
  • Patent number: 7256488
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: August 14, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaping Zhou, Chu-Chung Lee
  • Patent number: 7203608
    Abstract: A method for measuring impedance of a microprocessor chip, electronic packaging, and circuit board power supply system by generating a pseudo-impulse current having a width size in the time domain not larger than the inversion of a maximum frequency of interest and obtaining a voltage measurement in a frequency domain of the pseudo-impulse current. The mechanism of the present invention then predicts the normalized Fourier transformation of the current in the frequency domain, wherein the normalized Fourier transformation depends upon a switching charge of the pseudo-impulse current, measures the switching charge of the pseudo-impulse current, obtains a first current measurement at zero frequency using the measured switching charge, and obtains a second current measurement at a frequency of interest using the first current measurement.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: April 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Makoto Aikawa, Sang Hoo Dhong, Brian Flachs, Paul Marlan Harvey, Brad William Michael, Yaping Zhou
  • Publication number: 20060163716
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Application
    Filed: March 24, 2006
    Publication date: July 27, 2006
    Inventors: Yaping Zhou, Chu-Chung Lee
  • Patent number: 7049694
    Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: May 23, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yaping Zhou, Chu-Chung Lee