Patents by Inventor Yasuhiko Takemura

Yasuhiko Takemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10324115
    Abstract: Provided is a method for measuring a current that a component of a matrix device can supply. A device including components (pixels) arranged in a matrix, first wirings, and second wirings and third wirings which cross the first wirings is used. Each component includes a potential supply circuit, a transistor, and a capacitor.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 10249626
    Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 10228729
    Abstract: An electronic device includes a flexible display substrate including a transmission-type display region and a non-transmission-type display region, and the flexible display substrate is fixed on one or more of housings. Portion of the housing is transparent, and the transmission-type display region overlaps with this transparent portion. In addition, the non-transmission-type display region overlaps with opaque components such as an arithmetic processing unit, a battery, or the like stored in the housing. Display contents and display modes are used properly for the transmission-type display region and the non-transmission-type display region, thereby making it possible to display various images. Other embodiments are also claimed.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 10229913
    Abstract: A lookup table with low power consumption is provided. The lookup table includes a memory element including a transistor and a capacitor. A drain of the transistor is connected to one electrode of a capacitor and the input of an inverter, and a source is connected to a first wiring. The other electrode of the capacitor is connected to a second wiring. In such a memory element, the potential of the second wiring is complementary to the potential of the first wiring when writing data; accordingly, the potential of the drain of the transistor, i.e., the potential of the input of the inverter can be higher than the high potential of the inverter. Thus, shoot-through current of the inverter at this time can be significantly reduced. As a result, power consumption in a standby state can be significantly reduced.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: March 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Publication number: 20190044516
    Abstract: A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation.
    Type: Application
    Filed: October 1, 2018
    Publication date: February 7, 2019
    Inventor: Yasuhiko TAKEMURA
  • Patent number: 10135446
    Abstract: A semiconductor device using a programming unit with is provided. A highly reliable semiconductor device using the programming unit is provided. A highly integrated semiconductor device using the programming unit is provided. In a semiconductor circuit having a function of changing a structure of connections between logic cells such as PLDs, connection and disconnection between the logic cells or power supply to the logic cells is controlled by a programming unit using an insulated gate field-effect transistor with a small amount of off-state current or leakage current. A transfer gate circuit may be provided in the programming unit. To lower driving voltage, a capacitor may be provided in the programming unit and the potential of the capacitor may be changed during configuration and during operation.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: November 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 10044027
    Abstract: An object is to increase the conductivity of an electrode including active material particles and the like, which is used for a battery. Two-dimensional carbon including 1 to 10 graphenes is used as a conduction auxiliary agent, instead of a conventionally used conduction auxiliary agent extending only one-dimensionally at most, such as graphite particles, acetylene black, or carbon fibers. A conduction auxiliary agent extending two-dimensionally has higher probability of being in contact with active material particles or other conduction auxiliary agents, so that the conductivity can be improved.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Tamae Moriwaka
  • Publication number: 20180212154
    Abstract: A light-emitting element includes a light-emitting layer including a guest, an n-type host and a p-type host between a pair of electrodes, where the difference between the energy difference between a triplet excited state and a ground state of the n-type host (or p-type host) and the energy difference between a triplet excited state and a ground state of the guest is 0.15 eV or more. Alternatively, in such a light-emitting element, the LUMO level of the n-type host is higher than the LUMO level of the guest by 0.1 eV or more, or the HOMO level of the p-type host is lower than the HOMO level of the guest by 0.1 eV or more.
    Type: Application
    Filed: March 23, 2018
    Publication date: July 26, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi SEO, Nobuharu OHSAWA, Satoko SHITAGAKI, Hideko INOUE, Hiroshi KADOMA, Harue OSAKA, Kunihiko SUZUKI, Yasuhiko TAKEMURA
  • Publication number: 20180203046
    Abstract: Provided is a method for measuring a current that a component of a matrix device can supply. A device including components (pixels) arranged in a matrix, first wirings, and second wirings and third wirings which cross the first wirings is used. Each component includes a potential supply circuit, a transistor, and a capacitor.
    Type: Application
    Filed: September 15, 2015
    Publication date: July 19, 2018
    Inventor: Yasuhiko TAKEMURA
  • Patent number: 10013089
    Abstract: A semiconductor device having a novel data input and output panel with high definition is provided. A method for driving the semiconductor device having the novel data input and output panel with high definition is provided. The data input and output panel includes, over a substrate, proximity sensors, signal lines electrically connected to the proximity sensors, and pixels electrically connected to the signal lines. The signal lines can supply image signals to the pixels, can supply control signals to the proximity sensors, and can be supplied with sensing signals from the proximity sensors.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: July 3, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9929350
    Abstract: A light-emitting element includes a light-emitting layer including a guest, an n-type host and a p-type host between a pair of electrodes, where the difference between the energy difference between a triplet excited state and a ground state of the n-type host (or p-type host) and the energy difference between a triplet excited state and a ground state of the guest is 0.15 eV or more. Alternatively, in such a light-emitting element, the LUMO level of the n-type host is higher than the LUMO level of the guest by 0.1 eV or more, or the HOMO level of the p-type host is lower than the HOMO level of the guest by 0.1 eV or more.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: March 27, 2018
    Assignee: Semiconducor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Nobuharu Ohsawa, Satoko Shitagaki, Hideko Inoue, Hiroshi Kadoma, Harue Osaka, Kunihiko Suzuki, Yasuhiko Takemura
  • Patent number: 9911866
    Abstract: An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a second semiconductor layer including an i-type second oxide semiconductor is provided in contact with the other surface. The energy difference between a vacuum level and a Fermi level in the second oxide semiconductor is larger than that in the first oxide semiconductor. In the first semiconductor layer, a region in the vicinity of the junction surface with the second oxide semiconductor which satisfies the above condition is a region having an extremely low carrier concentration (a quasi-i-type region). By using the region as a channel, the off-state current can be reduced. Further, a drain current of the FET flows through the first oxide semiconductor having a high mobility; accordingly, a large amount of current can be extracted.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Publication number: 20180061376
    Abstract: Providing a new display device and a display method. When image data is sent from a processor to a display unit, the image data is divided into 2 or more parts such as a photographic picture and a non-picture, and corresponding compressed data is generated by performing a suitable compression processing. The size of each of the compressed data is reduced and is thus suitable to be sent to a display unit. Each of the compressed data is decompressed by a display driver; thus becoming decompressed data. Each of the decompressed data is used for display by the display unit. Other than numerical operation, a display unit having a reflective pixel and a self-luminous pixel may be used to combine the decompressed data.
    Type: Application
    Filed: August 21, 2017
    Publication date: March 1, 2018
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Yasuhiko TAKEMURA
  • Publication number: 20180033362
    Abstract: A display device includes a display portion where pixels including light-emitting elements are arranged in matrix and each of the pixels comprises at least a subpixel. A display method of the display device includes a step of calculating a first part watched by a user of the display device and a step of determining whether or not the first part is included in the display portion are included. In the case where the first part is included in the display portion, the gray level of first subpixels that are included in the first part is made different from the gray level of second subpixels that are included in the other part.
    Type: Application
    Filed: July 25, 2017
    Publication date: February 1, 2018
    Inventors: Shunpei YAMAZAKI, Yasuhiko TAKEMURA
  • Patent number: 9859443
    Abstract: Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Yasuhiko Takemura
  • Publication number: 20170373068
    Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
    Type: Application
    Filed: September 12, 2017
    Publication date: December 28, 2017
    Inventors: Shunpei YAMAZAKI, Yasuhiko TAKEMURA
  • Patent number: 9825042
    Abstract: In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit line MBL_. Each cell includes a sub bit line SBL_n_m and 4 to 64 memory cells (a memory cell CL_n_m_1 or the like). Further, each cell includes selection transistors STr1_n_m and STr2_n_m and an amplifier circuit AMP_n_m that is a complementary inverter or the like is connected to the selection transistor STr2_n_m. Since parasitic capacitance of the sub bit line SBL_n_m is sufficiently small, potential change due to electric charge in a capacitor of each memory cell can be amplified by the amplifier circuit AMP_n_m without an error, and can be output to the bit line.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9812560
    Abstract: Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: November 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9804719
    Abstract: The accuracy of reading characteristics or data of pixels or memory cells in a matrix device is increased. An electronic device includes a plurality of drive lines, a sense line intersecting the drive lines, a plurality of element devices provided at intersections thereof, a detecting circuit, a decoder, and a driver. The detecting circuit can detect a first physical quantity of the sense line and transmit a digital signal obtained by digitizing the first physical quantity to the decoder. Each of the element devices can change the first physical quantity of the sense line in accordance with a signal of the corresponding drive line. The driver can transmit coded signals based on a Hadamard matrix to the decoder and the drive lines. The decoder can perform arithmetic processing with use of the coded signals and the digital signal and calculate values based on second physical quantities of the element devices.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 9797931
    Abstract: To provide a measurement method of characteristics of an electrical element which causes variation in the luminance of pixels. In a device which includes components (pixels) arranged in a matrix and a wiring and where each component is capable of supplying current to the wiring through an electrical element included in each component, supply and non-supply of current of N components are individually set and current flowing through the wiring is measured N times. In the respective N measurements, combinations of the supply and non-supply of current in N components capable of supplying current to the wiring differ from one another. The amount of current flowing through each electrical element is obtained based on current obtained by the N measurements and the combinations of supply and non-supply of current in the N measurements.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: October 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Hiroyuki Miyake