Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.

Abstract: A semiconductor device including an oscillator configured to output a first signal, and circuitry configured to count a cycle number of the first signal OSC. Before the oscillator outputs an N-th (N is an integer equal to or larger than 2) cycle of the first signal, the circuitry changes a count value of the cycle number of the first signal to N.

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

Abstract: According to one embodiment, a semiconductor memory device includes a nonvolatile memory cell, a detection circuit which detects a first voltage and selects one of a first mode and a second mode based on the first voltage, and a transmitting unit which outputs a first signal corresponding to the one of the first mode and the second mode. The detection circuit selects the first mode when the first voltage is equal to or greater than a determination value, and selects the second mode when the first voltage is less than the determination value. The transmitting unit outputs the first signal of a first amplitude in the first mode, and outputs the first signal of a second amplitude that is smaller than the first amplitude in the second mode.

Abstract: A storage device includes a memory cell array, an input/output circuit, and a logic circuit. The input/output circuit including an input/output signal line through which data to be written into the memory cell array is received and data read from the memory cell array is transmitted. The logic circuit is configured to output a first signal to the input/output circuit. The first signal at an active level enables at least a part of the input/output circuit. The logic circuit includes a latch circuit configured to output a second signal at a level corresponding to a value of latched data. The logic circuit receives third, fourth, and fifth signals from an outside of the storage device via the input/output circuit. The logic circuit outputs a negative logical product of the third signal and a logical sum of at least the second, fourth, and fifth signals as the first signal.

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

Abstract: A semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first circuit configured to output a fourth signal based on a signal selected and output by the first select circuit; a first output buffer configured to output a fifth signal based on the signal selected and output by the first select circuit; a first output pad configured to externally output the fifth signal; and a counter configured to count a number of times the fourth signal is output.

Abstract: An amplifier of an input circuit includes: a first PMOS transistor having a gate connected to a first node, a source connected to a second node, and a drain connected to a third node; a second PMOS transistor having a gate connected to a fourth node that inputs a reference signal, a source connected to the second node, and a drain connected to a fifth node; a current source connected between a power supply voltage and the second node; a load circuit connected between the third node and a ground voltage; a first NMOS transistor having a gate connected to the first node, a drain connected to the power supply voltage, and a source connected to the fifth node; and a second NMOS transistor having a gate connected to the fourth node, a drain connected to the power supply voltage, and a source connected to the third node.

Abstract: According to one embodiment, a semiconductor memory device includes a first circuit configured to receive first bit data of an input signal, store, in a first latch circuit, first data based on the first bit data and a reference voltage, and output a first signal based on the first data, and a second circuit configured to receive second bit data of the input signal, store, in a second latch circuit, second data based on the second bit data and the reference voltage, and output a second signal based on the second data. The first circuit is configured to set the first latch circuit in a reset state based on the second signal. The second circuit is configured compare the second bit data and the reference voltage based on the first data and set the second latch circuit in a reset state based on the first signal.

Abstract: A semiconductor memory device includes a first pad, a clock generation circuit configured to generate a first clock, an output circuit configured to output the first clock through the first pad, a designation circuit configured to designate one of a plurality of contiguous times slots, each of which is set with respect to clock cycles of the first clock, and a peak control circuit configured to execute an operation that generates a current peak, at a timing corresponding to the designated time slot.

Abstract: A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.

Abstract: A memory system includes a memory chip and a memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller.

Abstract: According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.

Abstract: A semiconductor memory device includes a memory cell array, first and second pads, an interface circuit connected to the first pad and configured to transmit data input through the first pad to the memory cell array and output data received from the memory cell array through the first pad, a ZQ calibration circuit that is connected to the second pad and executes a ZQ calibration to generate a ZQ calibration value, and a sequencer configured to control the ZQ calibration circuit to apply the ZQ calibration value to the interface circuit. A command set is input through the first pad after reading data from the memory cell array to cause the interface circuit to output the data read from the memory cell array, and the ZQ calibration circuit executes the ZQ calibration after the command set is input and before the data is output through the first pad.

Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

Abstract: According to one embodiment, a semiconductor memory device includes: a first delay circuit configured to delay a first signal and provide a variable delay time; a first select circuit configured to select a second signal or a third signal based on the first signal delayed by the first delay circuit; a first output buffer configured to output a fourth signal based on a signal selected by the first select circuit; a first output pad configured to externally output the fourth signal; and a counter configured to count a number of times the fourth signal is output.

Abstract: A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variable registor resistor at different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.