Patents by Inventor Yasuhiro HIRASHIMA
Yasuhiro HIRASHIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200265902Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
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Publication number: 20200202959Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: ApplicationFiled: August 29, 2019Publication date: June 25, 2020Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yumi TAKADA, Yasuhiro HIRASHIMA, Satoshi INOUE, Kensuke YAMAMOTO, Shouichi OZAKI, Taichi WAKUI, Fumiya WATANABE
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Publication number: 20200185044Abstract: A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.Type: ApplicationFiled: August 30, 2019Publication date: June 11, 2020Inventors: Yumi TAKADA, Yasuhiro HIRASHIMA, Kenta SHIBASAKI, Yousuke HAGIWARA
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Patent number: 10679710Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: GrantFiled: September 2, 2018Date of Patent: June 9, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Hirashima, Masaru Koyanagi, Mikihiko Ito, Kei Shiraishi, Fumiya Watanabe
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Publication number: 20200127653Abstract: A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.Type: ApplicationFiled: December 20, 2019Publication date: April 23, 2020Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI
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Publication number: 20200014385Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: ApplicationFiled: September 13, 2019Publication date: January 9, 2020Inventors: Yasuhiro HIRASHIMA, Masaru Koyanagi, Yutaka Takayama
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Patent number: 10530350Abstract: A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.Type: GrantFiled: September 2, 2018Date of Patent: January 7, 2020Assignee: Toshiba Memory CorporationInventors: Yasuhiro Hirashima, Masaru Koyanagi
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Patent number: 10482977Abstract: A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.Type: GrantFiled: March 5, 2018Date of Patent: November 19, 2019Assignee: TOSHIBA MEMEORY CORPORATIONInventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yasuhiro Hirashima
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Patent number: 10461750Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: GrantFiled: February 27, 2018Date of Patent: October 29, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhiro Hirashima, Masaru Koyanagi, Yutaka Takayama
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Publication number: 20190296724Abstract: A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.Type: ApplicationFiled: September 2, 2018Publication date: September 26, 2019Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI
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Publication number: 20190295661Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.Type: ApplicationFiled: September 2, 2018Publication date: September 26, 2019Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
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Patent number: 10276218Abstract: A semiconductor memory device includes a plurality of memory chips that are stacked above one another and connected to each other through a through via, an interface chip that is connected to the plurality of memory chips, and a plurality of first terminals for connection with an external device. The interface chip includes a plurality of second terminals that are connected to the plurality of first terminals, and is capable of receiving a signal that is supplied from the external device through the first and second terminals, and stores configuration information according to which a set number of the second terminals are designated for receiving control signals for the plurality of memory chips.Type: GrantFiled: February 26, 2018Date of Patent: April 30, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhiro Hirashima, Mami Kakoi, Shinya Okuno
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Publication number: 20190080769Abstract: A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.Type: ApplicationFiled: March 5, 2018Publication date: March 14, 2019Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yasuhiro HIRASHIMA
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Publication number: 20190007045Abstract: A semiconductor device includes a latch circuit including a first inverter configured to output a first signal based on an input signal, a second inverter configured to output a first clock signal based on a first strobe signal, a third inverter configured to output a second clock signal based on a second strobe signal, a first clock generation circuit configured to generate a third clock signal having transitions that are delayed with respect to the first clock signal, a second clock generation circuit configured to generate a fourth clock signal having transitions that are delayed with respect to the second clock signal, a fourth inverter configured to output an inversion signal of the first signal in accordance with the third and fourth clock signals, and a data latch circuit configured to latch an output signal of the fourth inverter.Type: ApplicationFiled: February 27, 2018Publication date: January 3, 2019Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI, Yutaka TAKAYAMA
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Publication number: 20180261260Abstract: A semiconductor memory device includes a plurality of memory chips that are stacked above one another and connected to each other through a through via, an interface chip that is connected to the plurality of memory chips, and a plurality of first terminals for connection with an external device. The interface chip includes a plurality of second terminals that are connected to the plurality of first terminals, and is capable of receiving a signal that is supplied from the external device through the first and second terminals, and stores configuration information according to which a set number of the second terminals are designated for receiving control signals for the plurality of memory chips.Type: ApplicationFiled: February 26, 2018Publication date: September 13, 2018Inventors: Yasuhiro HIRASHIMA, Mami KAKOI, Shinya OKUNO
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Patent number: 9792983Abstract: A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variable registor at different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.Type: GrantFiled: May 31, 2016Date of Patent: October 17, 2017Assignee: Toshiba Memory CorporationInventors: Yasuhiro Hirashima, Masaru Koyanagi
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Patent number: 9679617Abstract: According to one embodiment, an amplifier includes a first inverter which inverts and delays a first signal to generate a second signal. A second inverter inverts and delays a third signal to generate a fourth signal. A first transistor includes a gate electrode supplied with the second signal. A second transistor includes a gate electrode supplied with the fourth signal. An output terminal is coupled to one terminal of the second transistor and outputs a fifth signal. A third inverter inverts and delays the fifth signal to generate a sixth signal. A first discharge circuit discharges one terminal of the first transistor and the one terminal of the second transistor based on the first, sixth, or fourth signal, and includes one terminal coupled to the other terminal of each of the first and second transistors.Type: GrantFiled: June 14, 2016Date of Patent: June 13, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yohei Yasuda, Hiromitsu Komai, Kensuke Yamamoto, Masaru Koyanagi, Yasuhiro Hirashima
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Publication number: 20170125092Abstract: A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variable resister at different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.Type: ApplicationFiled: May 31, 2016Publication date: May 4, 2017Inventors: Yasuhiro HIRASHIMA, Masaru KOYANAGI
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Publication number: 20170084313Abstract: According to one embodiment, an amplifier includes a first inverter which inverts and delays a first signal to generate a second signal. A second inverter inverts and delays a third signal to generate a fourth signal. A first transistor includes a gate electrode supplied with the second signal. A second transistor includes a gate electrode supplied with the fourth signal. An output terminal is coupled to one terminal of the second transistor and outputs a fifth signal. A third inverter inverts and delays the fifth signal to generate a sixth signal. A first discharge circuit discharges one terminal of the first transistor and the one terminal of the second transistor based on the first, sixth, or fourth signal, and includes one terminal coupled to the other terminal of each of the first and second transistors.Type: ApplicationFiled: June 14, 2016Publication date: March 23, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yohei YASUDA, Hiromitsu KOMAI, Kensuke YAMAMOTO, Masaru KOYANAGI, Yasuhiro HIRASHIMA
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Patent number: 9230671Abstract: According to one embodiment, there is provided an output circuit including a driver transistor and a pre-driver circuit. The driver transistor is connected to an output terminal. The pre-driver circuit is configured to turn ON/OFF the driver transistor. The pre-driver circuit includes a first transistor, a second transistor, a third transistor. The first transistor is configured to control ON speed of the driver transistor. The second transistor is connected in parallel with the first transistor. The second transistor is configured to control ON speed of the driver transistor. The third transistor is connected in parallel with the first transistor and in series with the second transistor. The third transistor is configured to activate or deactivate the second transistor.Type: GrantFiled: March 7, 2014Date of Patent: January 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Hirashima, Masaru Koyanagi