Abstract: According to one embodiment, there is provided an output circuit including a driver transistor and a pre-driver circuit. The driver transistor is connected to an output terminal. The pre-driver circuit is configured to turn ON/OFF the driver transistor. The pre-driver circuit includes a first transistor, a second transistor, a third transistor. The first transistor is configured to control ON speed of the driver transistor. The second transistor is connected in parallel with the first transistor. The second transistor is configured to control ON speed of the driver transistor. The third transistor is connected in parallel with the first transistor and in series with the second transistor. The third transistor is configured to activate or deactivate the second transistor.

Abstract: The receiving apparatus according to the present invention includes a multi-phase clock generating circuit, a latch component, an error check component, and a selector circuit. The multi-phase clock generating circuit generates a plurality of clocks, phases of which are different from each other. The latch component receives an external data divided into two or more and the plurality of the clocks, and concurrently obtains a plurality of data, clock-timing of which is different from each other, by latching the external data by different clocks. The error check component detects an error of the respective data. The selector circuit selects data judged as no-error data from the plurality of the data, and outputs the selected data as received data. According to the circuit configuration like this, it is possible to precisely receive the data.