Patents by Inventor Yasuhiro Kimura
Yasuhiro Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145091Abstract: Provided herein is a method for modulating the amount of virus in a subject comprising administering to the subject an agent for controlling an indicator associated with a D-amino acid in the subject.Type: ApplicationFiled: October 17, 2023Publication date: May 2, 2024Applicants: National Institutes of Biomedical Innovation, Health and Nutrition, Kagami Inc.Inventors: Tomonori KIMURA, Shihoko KIMURA, Yasuhiro YASUTOMI, Masamitsu ASAKA, Emiko URANO, Daichi UTSUMI, Masashi MITA
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Patent number: 11913828Abstract: A test object includes a sensor housing for vibrating together with a test object in synchronism with vibration of the test object; a piezoelectric substrate for vibrating together with the sensor housing in synchronism with vibration of the sensor housing, where a first interdigital electrode, a first terminal, a second interdigital electrode, and a second terminal are disposed on a first surface of the piezoelectric substrate, and the piezoelectric substrate is disposed inside the sensor housing to be fixed to the sensor housing; an amplifier for receiving a signal output from the second terminal as an input signal, amplifying the received input signal, and transmitting the input signal after the amplification to the first terminal as an output signal; a deformable layer being elastic and having a first surface adhered to a second surface of the piezoelectric substrate; and a heavy object having a first surface adhered to a second surface of the deformable layer.Type: GrantFiled: October 19, 2021Date of Patent: February 27, 2024Assignee: Mitsubishi Electric CorporationInventors: Rokuzo Hara, Tomonori Kimura, Koji Ibata, Yasuhiro Nishioka
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Patent number: 10964785Abstract: The object of the present invention is to enhance the device yield of SiC epitaxial wafers. The SiC epitaxial wafer includes a drift layer which is a SiC epitaxial layer. The drift layer has a film thickness of 18 ?m or more and 350 ?m or less and has arithmetic average roughness of 0.60 nm or more and 3.00 nm or less, and the impurity concentration thereof is 1×1014/cm3 or more and 5×1015/cm3 or less.Type: GrantFiled: January 18, 2018Date of Patent: March 30, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoichiro Mitani, Yasuhiro Kimura, Akihito Ono
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Patent number: 10950435Abstract: A SiC substrate (1) has an off angle ?°. A SiC epitaxial layer (2) having a film thickness of Tm ?m is provided on the SiC substrate (1). Triangular defects (3) are formed on a surface of the SiC epitaxial layer (2). A density of triangular defects (3) having a length of Tm/Tan ?×0.9 or more in a substrate off direction is denoted by A. A density of triangular (3) defects having a length smaller than Tm/Tan ?×0.9 in the substrate off direction is denoted by B. B/A?0.5 is satisfied.Type: GrantFiled: April 6, 2017Date of Patent: March 16, 2021Assignee: Mitsubishi Electric CorporationInventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Yasuhiro Kimura, Yoichiro Mitani
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Patent number: 10910218Abstract: A SiC substrate (1) has an off angle ?°. A SiC epitaxial layer (2) having a film thickness of Tm ?m is provided on the SiC substrate (1). Triangular defects (3) are formed on a surface of the SiC epitaxial layer (2). A density of triangular defects (3) having a length of Tm/Tan ?×0.9 or more in a substrate off direction is denoted by A. A density of triangular (3) defects having a length smaller than Tm/Tan ?×0.9 in the substrate off direction is denoted by B. B/A?0.5 is satisfied.Type: GrantFiled: April 6, 2017Date of Patent: February 2, 2021Assignee: Mitsubishi Electric CorporationInventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Yasuhiro Kimura, Yoichiro Mitani
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Patent number: 10858757Abstract: An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.Type: GrantFiled: May 9, 2017Date of Patent: December 8, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Takanori Tanaka, Shigehisa Yamamoto, Yu Nakamura, Yasuhiro Kimura, Shuhei Nakata, Yoichiro Mitani
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Patent number: 10837447Abstract: [Object] To efficiently supply lubricant oil to a bearing member with a simple mechanism. [Solving Means] A vacuum pump includes a first housing, a second housing, a rotor shaft, a lubricant oil-stirring plate, and a bearing member. The second housing is attached to the first housing and forms a space that stores lubricant oil together with the first housing. The rotor shaft passes through the first housing. The lubricant oil-stirring plate is housed in the space and is attached to the rotor shaft. The bearing member is fixed to the first housing and rotatably supports the rotor shaft. The first housing includes a supply port that enables lubricant oil to be supplied to the bearing member. The second housing includes an inner-wall upper portion which the lubricant oil stirred by the lubricant oil-stirring plate hits against. The inner-wall upper portion of the second housing includes a recess portion that enables the lubricant oil to move above the supply port.Type: GrantFiled: May 30, 2018Date of Patent: November 17, 2020Assignee: ULVAC, INC.Inventors: Yasuhiro Kimura, Shinnosuke Tokuhira, Hideaki Inoue, Kenji Machiya
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Publication number: 20200271120Abstract: A vacuum pump according to an embodiment of the present invention includes a pump main body, a first temperature sensor, a motor, and a control unit. The pump main body includes a rotary shaft and a metal casing portion. The first temperature sensor is attached to the casing portion and detects a temperature of the casing portion. The motor includes a rotor core including a permanent magnet and attached to the rotary shaft, a stator core including a plurality of coils, and a can that houses the rotor core. The control unit includes a driving circuit and a correcting circuit. The driving circuit supplies the plurality of coils with a driving signal for rotating the motor on a basis of a pre-set induced voltage constant. The correcting circuit corrects the induced voltage constant on a basis of an output of the first temperature sensor.Type: ApplicationFiled: June 20, 2018Publication date: August 27, 2020Inventors: Yasuhiro KIMURA, Kenji MACHIYA, Shinnosuke TOKUHIRA, Hideaki INOUE
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Publication number: 20200240412Abstract: [Object] To efficiently supply lubricant oil to a bearing member with a simple mechanism. [Solving Means] A vacuum pump includes a first housing, a second housing, a rotor shaft, a lubricant oil-stirring plate, and a bearing member. The second housing is attached to the first housing and forms a space that stores lubricant oil together with the first housing. The rotor shaft passes through the first housing. The lubricant oil-stirring plate is housed in the space and is attached to the rotor shaft. The bearing member is fixed to the first housing and rotatably supports the rotor shaft. The first housing includes a supply port that enables lubricant oil to be supplied to the bearing member. The second housing includes an inner-wall upper portion which the lubricant oil stirred by the lubricant oil-stirring plate hits against. The inner-wall upper portion of the second housing includes a recess portion that enables the lubricant oil to move above the supply port.Type: ApplicationFiled: May 30, 2018Publication date: July 30, 2020Inventors: Yasuhiro KIMURA, Shinnosuke TOKUHIRA, Hideaki INOUE, Kenji MACHIYA
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Patent number: 10707075Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.Type: GrantFiled: November 28, 2016Date of Patent: July 7, 2020Assignee: Mitsubishi Electric CorporationInventors: Kenichi Hamano, Akihito Ohno, Takuma Mizobe, Masashi Sakai, Yasuhiro Kimura, Yoichiro Mitani, Takashi Kanazawa
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Publication number: 20200144053Abstract: A semiconductor wafer includes a silicon carbide substrate having a first carrier concentration, a carrier concentration transition layer, and an epitaxial layer provided on the carrier concentration transition layer, the epitaxial layer having a second carrier concentration, and the second carrier concentration being lower than the first carrier concentration. The carrier concentration transition layer has a concentration gradient in the thickness direction. The carrier concentration decreases as the film thickness increases from an interface between a layer directly below the carrier concentration transition layer and the carrier concentration transition layer, and the carrier concentration decreases at a lower rate of decrease as the film thickness of the carrier concentration transition layer increases.Type: ApplicationFiled: November 28, 2016Publication date: May 7, 2020Applicant: Mitsubishi Electric CorporationInventors: Kenichi HAMANO, Akihito OHNO, Takuma MIZOBE, Masashi SAKAI, Yasuhiro KIMURA, Yoichiro MITANI, Takashi KANAZAWA
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Publication number: 20200066847Abstract: The object of the present invention is to enhance the device yield of SiC epitaxial wafers. The SiC epitaxial wafer includes a drift layer which is a SiC epitaxial layer. The drift layer has a film thickness of 18 ?m or more and 350 ?m or less and has arithmetic average roughness of 0.60 nm or more and 3.00 nm or less, and the impurity concentration thereof is 1×1014/cm3 or more and 5×1015/cm3 or less.Type: ApplicationFiled: January 18, 2018Publication date: February 27, 2020Applicant: Mitsubishi Electric CorporationInventors: Yoichiro MITANI, Yasuhiro KIMURA, Akihito ONO
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Patent number: 10559508Abstract: A method for manufacturing an SiC substrate includes: performing a CMP treatment on an SiC substrate; after the CMP treatment, capturing an image of a surface of the SiC substrate to detect a scratch; determining the SiC substrate as a good article when a length L of the scratch having a contrast value equal to or larger than a threshold value is not more than ?(D/2)2/A×F/100, wherein the scratch having the contrast value equal to or larger than the threshold value in the image serves as a starting point of an epitaxial defect, a diameter of the SiC substrate is represented by D, a length of a long side of a device chip to be formed on the SiC substrate is represented by A, and an allowable defective rate caused by scratches is represented by F.Type: GrantFiled: December 4, 2018Date of Patent: February 11, 2020Assignee: Mitsubishi Electric CorporationInventor: Yasuhiro Kimura
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Publication number: 20200020528Abstract: A SiC substrate (1) has an off angle ?°. A SiC epitaxial layer (2) having a film thickness of Tm ?m is provided on the SiC substrate (1). Triangular defects (3) are formed on a surface of the SiC epitaxial layer (2). A density of triangular defects (3) having a length of Tm/Tan ?×0.9 or more in a substrate off direction is denoted by A. A density of triangular (3) defects having a length smaller than Tm/Tan ?×0.9 in the substrate off direction is denoted by B. B/A?0.5 is satisfied.Type: ApplicationFiled: April 6, 2017Publication date: January 16, 2020Applicant: Mitsubishi Electric CorporationInventors: Kenichi HAMANO, Akihito OHNO, Takuma MIZOBE, Yasuhiro KIMURA, Yoichiro MITANI
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Publication number: 20190355629Abstract: A method for manufacturing an SiC substrate includes: performing a CMP treatment on an SiC substrate; after the CMP treatment, capturing an image of a surface of the SiC substrate to detect a scratch; determining the SiC substrate as a good article when a length L of the scratch having a contrast value equal to or larger than a threshold value is not more than ?(D/2)2/A×F/100, wherein the scratch having the contrast value equal to or larger than the threshold value in the image serves as a starting point of an epitaxial defect, a diameter of the SiC substrate is represented by D, a length of a long side of a device chip to be formed on the SiC substrate is represented by A, and an allowable defective rate caused by scratches is represented by F.Type: ApplicationFiled: December 4, 2018Publication date: November 21, 2019Applicant: Mitsubishi Electric CorporationInventor: Yasuhiro Kimura
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Publication number: 20190145021Abstract: An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.Type: ApplicationFiled: May 9, 2017Publication date: May 16, 2019Applicant: Mitsubishi Electric CorporationInventors: Takanori TANAKA, Shigehisa YAMAMOTO, Yu NAKAMURA, Yasuhiro KIMURA, Shuhei NAKATA, Yoichiro MITANI
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Publication number: 20170040166Abstract: A manufacturing method for manufacturing a silicon carbide epitaxial wafer includes: introducing a cleaning gas into a growth furnace to remove dendrite-like polycrystal of silicon carbide attached to an inner wall of the growth furnace; after introducing the cleaning gas, bringing a silicon carbide substrate in the growth furnace; and growing a silicon carbide epitaxial layer on the silicon carbide substrate by introducing a processing gas into the growth furnace to manufacture a silicon carbide epitaxial wafer, wherein the cleaning gas having fluid energy of 1.6E?4 [J] or higher is introduced into the growth furnace.Type: ApplicationFiled: April 5, 2016Publication date: February 9, 2017Applicant: Mitsubishi Electric CorporationInventors: Akihito OHNO, Masashi SAKAI, Yoichiro MITANI, Takahiro YAMAMOTO, Yasuhiro KIMURA, Takuma MIZOBE, Nobuyuki TOMITA
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Patent number: 9564315Abstract: A manufacturing method for manufacturing a silicon carbide epitaxial wafer includes: introducing a cleaning gas into a growth furnace to remove dendrite-like polycrystal of silicon carbide attached to an inner wall of the growth furnace; after introducing the cleaning gas, bringing a silicon carbide substrate in the growth furnace; and growing a silicon carbide epitaxial layer on the silicon carbide substrate by introducing a processing gas into the growth furnace to manufacture a silicon carbide epitaxial wafer, wherein the cleaning gas having fluid energy of 1.6E-4 [J] or higher is introduced into the growth furnace.Type: GrantFiled: April 5, 2016Date of Patent: February 7, 2017Assignee: Mitsubishi Electric CorporationInventors: Akihito Ohno, Masashi Sakai, Yoichiro Mitani, Takahiro Yamamoto, Yasuhiro Kimura, Takuma Mizobe, Nobuyuki Tomita
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Patent number: 8549388Abstract: According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.Type: GrantFiled: February 25, 2011Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Fukutomi, Hiroshi Yao, Shinichi Kanno, Shigehiro Asano, Toshikatsu Hida, Yasuhiro Kimura
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Patent number: 8463986Abstract: A plurality of free-block management lists for respectively managing a logical block with a same bank number, a same chip number, and a same plane number as a free block, and a free block selecting unit that selects a required number of free-block management lists from the free-block management lists to obtain a free block from the selected free-block management lists are provided.Type: GrantFiled: August 12, 2011Date of Patent: June 11, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hajime Yamazaki, Yasuhiro Kimura, Hiroshi Yao