Patents by Inventor Yasuhiro Uemoto

Yasuhiro Uemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6294438
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: September 25, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Publication number: 20010019874
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Application
    Filed: January 24, 2001
    Publication date: September 6, 2001
    Applicant: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6232131
    Abstract: The method for manufacturing a semiconductor device of this invention comprises the steps: forming a first wiring layer on a semiconductor substrate on which a capacitor element with a capacitor dielectric film is formed, and the capacitor dielectric film is at least one film selected from the group consisting of a capacitor dielectric film with high dielectric constant and a ferroelectric film; conducting a first annealing to said semiconductor substrate; forming a second wiring layer on said first wiring layer; etching selectively the first wiring layer and the second wiring layer; and conducting a second annealing to the semiconductor substrate, so that the stress provided to the capacitor element can be reduced by annealing after forming each wiring layer, and thus, it can prevent the increase of leakage current and deterioration of dielectric breakdown voltage of the capacitor element having a capacitor dielectric film comprising a high capacitor dielectric film and a ferroelectric film.
    Type: Grant
    Filed: June 24, 1998
    Date of Patent: May 15, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Eiji Fujii, Yasuhiro Uemoto
  • Patent number: 6214660
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: April 10, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eigi Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6204111
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: March 20, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6174822
    Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: January 16, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Toshie Kutsunai, Yuji Judai, Yasuhiro Uemoto, Eiji Fujii
  • Patent number: 6169304
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6143597
    Abstract: A method of manufacturing a capacitor comprises a step of forming a first dielectric layer composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode, a step of sintering the first dielectric layer, a step of forming a second dielectric layer on the first dielectric layer, and a step of forming a second electrode on the second dielectric layer. By forming the second dielectric layer having small crystal grain size on the first dielectric layer having large crystal grain size, the surface of the capacitor insulating layer becomes flat.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: November 7, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Akihiro Matsuda, Yoshihisa Nagano, Toru Nasu, Koji Arita, Yasuhiro Uemoto
  • Patent number: 6126752
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: October 3, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 6107657
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: August 22, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6080617
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: June 27, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 6046490
    Abstract: A semiconductor device is provided with a multilayered interconnection and a capacitor dielectric element, in which the transistor in the device has a non-degraded characteristics and the degradation of the capacitor dielectric element is suppressed. The semiconductor device has wiring layers connecting to one another through contact holes in insulating layers. One of the insulating layers is formed so as to cover at least a part of the area above the transistor and so as not to cover the area above the capacitor dielectric element. Hydrogen generated by heat-treating the insulating layer is supplied to the transistor to recover the damage in it, while hydrogen is suppressed from arriving at the capacitor element so that the capacitor dielectric element does not degrade.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: April 4, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Uemoto, Yoshihisa Nagano, Akihiro Matsuda
  • Patent number: 6033920
    Abstract: This invention relates to a semiconductor device with embedded capacitor elements of which capacitor insulation layer is made of ferroelectric layer or dielectric layer of high dielectric constant, and its manufacturing method. This invention is made in order to solve the problems of rapid increase of leak current of capacitor element and the poor reliability caused by the large deviation of crystal sizes of conventional capacitor insulation layer of capacitor element incorporated in the semiconductor device.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: March 7, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Shimada, Yasuhiro Uemoto, Atsuo Inoue, Taketoshi Matsuura, Masamichi Azuma
  • Patent number: 6015987
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 5929475
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: July 27, 1999
    Inventors: Yasuhiro Uemoto, Eigi Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 5828098
    Abstract: This invention relates to a semiconductor device with embedded capacitor elements of which capacitor insulation layer is made of ferroelectric layer or dielectric layer of high dielectric constant, and its manufacturing method. This invention is made in order to solve the problems of rapid increase of leak current of capacitor element and the poor reliability caused by the large deviation of crystal sizes of conventional capacitor insulation layer of capacitor element incorporated in the semiconductor device.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: October 27, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Shimada, Yasuhiro Uemoto, Atsuo Inoue, Taketoshi Matsuura, Masamichi Azuma
  • Patent number: 5780351
    Abstract: A semi conductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: July 14, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 5717233
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: January 6, 1997
    Date of Patent: February 10, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 5661319
    Abstract: This is a semiconductor device having an integrated circuit and a capacitor formed on a semiconductor substrate. The capacitor comprises a bottom electrode serving also as a part of a diffusion layer of the integrated circuit, a dielectric film being formed on the bottom electrode, and a top electrode of a conductive film being formed on the dielectric film. In particular, it is preferred to form the dielectric film in two layers of dielectric film, and compose the dielectric film contacting with the bottom electrode of a dielectric material in a composition possessing an excess of a metal element than the stoichiometric composition.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: August 26, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Tooru Nasu, Akihiro Matsuda, Tatsuo Ootsuki
  • Patent number: 5624864
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: April 29, 1997
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki