Patents by Inventor Yasuhiro Uemoto

Yasuhiro Uemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080149965
    Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.
    Type: Application
    Filed: November 14, 2007
    Publication date: June 26, 2008
    Inventors: Kazuhiro KAIBARA, Masahiro HIKITA, Tetsuzo UEDA, Yasuhiro UEMOTO, Tsuyoshi TANAKA
  • Publication number: 20080149940
    Abstract: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced apart from each other on an active region in the nitride semiconductor layer. An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface. A first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 26, 2008
    Inventors: Daisuke SHIBATA, Kazushi Nakazawa, Masahiro Hikita, Yasuhiro Uemoto, Tetsuzo Ueda, Manabu Yanagihara, Tsuyoshi Tanaka
  • Publication number: 20080143421
    Abstract: A bidirectional switch comprises a first FET, a second FET, and a switch controller for controlling a conductive state in which current from a bidirectional power supply electrically connected to drain terminals bidirectionally flows, and a nonconductive state in which the current does not flow. In the conductive state, the switch controller applies, to gate terminals of the first FET and the second FET, a voltage higher than a threshold voltage with reference to a potential at a node to which source terminals of the first FET and the second FET are connected. In the nonconductive state, the switch controller causes the bidirectional power supply and each gate terminal to be electrically insulated from each other, and applies a voltage lower than or equal to the threshold voltage with reference to the potential at the node.
    Type: Application
    Filed: November 2, 2007
    Publication date: June 19, 2008
    Inventors: Manabu Yanagihara, Tatsuo Morita, Yasuhiro Uemoto
  • Patent number: 7375407
    Abstract: A Schottky barrier diode includes a first semiconductor layer and a second semiconductor layer successively formed above a substrate; and a high-resistance region formed in the first semiconductor layer and the second semiconductor layer and having higher resistance than the first semiconductor layer and the second semiconductor layer. A Schottky electrode and an ohmic electrode spaced from each other are formed on the second semiconductor layer in a portion surrounded with the high-resistance region.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: May 20, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
  • Publication number: 20080087915
    Abstract: A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.
    Type: Application
    Filed: July 24, 2007
    Publication date: April 17, 2008
    Inventors: Yasuhiro Uemoto, Masahiro Hikita, Tetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda
  • Publication number: 20080079023
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
    Type: Application
    Filed: August 7, 2007
    Publication date: April 3, 2008
    Inventors: Masahiro Hikita, Tetsuzo Ueda, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20080067546
    Abstract: A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 20, 2008
    Inventors: Tomohiro MURATA, Hiroaki UENO, Hidetoshi ISHIDA, Tetsuzo UEDA, Yasuhiro UEMOTO, Tsuyoshi TANAKA, Daisuke UEDA
  • Patent number: 7339207
    Abstract: A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1?xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1?N; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: March 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomohiro Murata, Yutaka Hirose, Yoshito Ikeda, Tsuyoshi Tanaka, Kaoru Inoue, Daisuke Ueda, Yasuhiro Uemoto
  • Publication number: 20070284653
    Abstract: A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group Ill-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.
    Type: Application
    Filed: April 20, 2007
    Publication date: December 13, 2007
    Inventors: Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Patent number: 7291872
    Abstract: In the structure of a semiconductor device of the present invention, a first source electrode is connected to a conductive substrate through a via hole, and a second source electrode is formed. Thus, even if a high reverse voltage is applied between a gate electrode and a drain electrode, electric field concentration likely to occur at an edge of the gate electrode closer to the drain electrode can be effectively dispersed or relaxed. Moreover, the conductive substrate is used as a substrate for forming element formation layers, so that a via hole penetrating the substrate to reach the backside thereof does not have to be formed in the conductive substrate. Thus, with the strength necessary for the conductive substrate maintained, the first source electrode can be electrically connected to a backside electrode.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: November 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Hikita, Hiroaki Ueno, Yutaka Hirose, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20070254419
    Abstract: A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.
    Type: Application
    Filed: June 26, 2007
    Publication date: November 1, 2007
    Applicant: MATSUSHIDA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Atsuhiko Kanda, Tsuyoshi Tanaka, Yasuhiro Uemoto, Yutaka Hirose, Tomohiro Murata
  • Publication number: 20070235768
    Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 11, 2007
    Inventors: Kazushi Nakazawa, Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20070210332
    Abstract: It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform.
    Type: Application
    Filed: March 2, 2007
    Publication date: September 13, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroaki UENO, Tetsuzo Ueda, Yasuhiro Uemoto, Daisuke Ueda, Tsuyoshi Tanaka, Manabu Yanagihara, Yutaka Hirose, Masahiro Hikita
  • Publication number: 20070176215
    Abstract: A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.
    Type: Application
    Filed: November 16, 2006
    Publication date: August 2, 2007
    Inventors: Manabu Yanagihara, Masahiro Hikita, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20070170463
    Abstract: A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 26, 2007
    Inventors: Hiroaki Ueno, Manabu Yanagihara, Tetsuzo Ueda, Yasuhiro Uemoto, Tsuyoshi Tanaka, Daisuke Ueda
  • Patent number: 7247891
    Abstract: A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: July 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsuhiko Kanda, Tsuyoshi Tanaka, Yasuhiro Uemoto, Yutaka Hirose, Tomohiro Murata
  • Patent number: 7241703
    Abstract: A method of forming films in a semiconductor device that can appropriately control a resistance value of a thin film resistance on an ozone TEOS film while preventing a metal thin film from remaining around a surface step unit after the metal thin film was dry etched. First, as shown in FIG. 1A, a step unit with the height of about 1 ?m is formed by forming elements such as HBT on a semiconductor substrate made up of semi-insulating GaAs. Next, as shown in FIG. 1B, a first ozone TEOS film with the thickness of 900 nm by a Normal pressure CVD method using mixed gas of tetraethoxysilane with ozone. Then, a second ozone TEOS film with the thickness of 100 nm is formed by reducing the ozone concentration to 10 g/m3, while maintaining the substrate temperature at 350° C.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: July 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiro Hikita, Yasuhiro Uemoto
  • Patent number: 7238970
    Abstract: A semiconductor device of the present invention comprises a Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity and at least one ohmic electrode formed on the Group III-V nitride semiconductor layer of gallium nitride or the like having n-type conductivity. The ohmic electrode is formed of a conductive material containing a metal boride.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: July 3, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Hirose, Tsuyoshi Tanaka, Yasuhiro Uemoto
  • Publication number: 20070126026
    Abstract: A semiconductor device includes: a first group-III nitride semiconductor layer formed on a substrate; a second group-III nitride semiconductor layer made of a single layer or two or more layers, formed on the first group-III nitride semiconductor layer, and acting as a barrier layer; a source electrode, a drain electrode, and a gate electrode formed on the second group-III nitride semiconductor layer, the gate electrode controlling a current flowing between the source and drain electrodes; and a heat radiation film with high thermal conductivity which covers, as a surface passivation film, the entire surface other than a bonding pad.
    Type: Application
    Filed: November 6, 2006
    Publication date: June 7, 2007
    Inventors: Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20070126115
    Abstract: A package substrate has a substrate body on which an electronic component is mounted. The substrate body is formed at its top or back surface with a diamond film, a diamond-like carbon film or a carbon film.
    Type: Application
    Filed: November 7, 2006
    Publication date: June 7, 2007
    Inventors: Manabu Yanagihara, Hiroaki Ueno, Yasuhiro Uemoto, Tsuyoshi Tanaka