Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

Abstract: A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlxGa1-xN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlyGa1-yN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

Abstract: A method of forming films in a semiconductor device that can appropriately control a resistance value of a thin film resistance on an ozone TEOS film while preventing a metal thin film from remaining around a surface step unit after the metal thin film was dry etched. First, as shown in FIG. 1A, a step unit with the height of about 1 &mgr;m is formed by forming elements such as HBT on a semiconductor substrate made up of semi-insulating GaAs. Next, as shown in FIG. 1B, a first ozone TEOS film with the thickness of 900 nm by a Normal pressure CVD method using mixed gas of tetraethoxysilane with ozone. Then, a second ozone TEOS film with the thickness of 100 nm is formed by reducing the ozone concentration to 10 g/m3, while maintaining the substrate temperature at 350° C.

Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Abstract: A trench isolation region separating active regions in which MISFETs are formed includes: side insulating films covering the sides of a trench; polycrystalline semiconductor layers of a first conductivity type covering the respective sides of the side insulating films, and a polycrystalline semiconductor layer of a second conductivity type filling a gap between the polycrystalline semiconductor layers of the first conductivity type. Two pn junctions extending along the depth direction of the trench are formed between each of the polycrystalline semiconductor layers of the first conductivity type and the polycrystalline semiconductor layer of the second conductivity type. Upon application of a voltage between the active regions, a depletion layer expands in one of the pn junctions, so that the voltage is also partly applied to the depletion layer. As a result, the concentration of electric field in the side insulating films is relaxed.

Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mate

Abstract: In an SOI (Silicon On Insulator) semiconductor device, a first semiconductor layer overlies a semiconductor substrate so as to sandwich an insulating layer, and second and third semiconductor layers with a different conductivity type from the second semiconductor layer are formed on the surface of the first semiconductor layer. At the interface between the first semiconductor layer and the insulating layer, a fourth semiconductor layer with a different conductivity type from the first semiconductor layer is formed. The fourth semiconductor layer includes an impurity of larger than 3×1012/cm2 so as not to be completely depleted even though a reverse bias voltage is applied between the second and third semiconductor layers.

Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mate

Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

Abstract: A semiconductor memory includes plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate. The plural lower electrodes are respectively connected with source regions of the plural transistors.

Abstract: A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100° C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700° C. for a barrier thickness of about 1000 Å and about 800° C. for a barrier thickness of about 3000 Å. The barrier layer is 800 Å thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.

Abstract: A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

Abstract: In a semiconductor layer formed on a first insulating film is formed an element isolation groove extending to the first insulating film. Thereafter, a second insulating film is deposited in the element isolation groove by using a vapor deposition method.

Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mate

Abstract: A semiconductor memory includes plural lower electrodes formed on a semiconductor substrate; a capacitor dielectric film of an insulating metal oxide continuously formed over the plural lower electrodes; plural upper electrodes formed on the capacitor dielectric film in positions respectively corresponding to the plural lower electrodes; and plural transistors formed on the semiconductor substrate. The plural lower electrodes are respectively connected with source regions of the plural transistors.

Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Abstract: The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 &mgr;m to 14 &mgr;m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collision of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.