Patents by Inventor Yasumasa Yamane

Yasumasa Yamane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190139783
    Abstract: A semiconductor device having high reliability is provided.
    Type: Application
    Filed: April 11, 2017
    Publication date: May 9, 2019
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Kazutaka KURIKI, Yuji EGI, Noritaka ISHIHARA, Yusuke NONAKA, Yasumasa YAMANE, Ryo TOKUMARU, Daisuke MATSUBAYASHI
  • Patent number: 10236357
    Abstract: A semiconductor device having stable electrical characteristics is provided. A semiconductor device that can be miniaturized or highly integrated is provided. One embodiment of the present invention includes a transistor including an oxide, a first barrier layer over the transistor, and a second barrier layer in contact with the first barrier layer. The oxide is in contact with an insulator including an excess-oxygen region. The insulator is in contact with the first barrier layer. The first barrier layer has a thickness greater than or equal to 0.5 nm and less than or equal to 1.5 nm. The second barrier layer is thicker than the first barrier layer.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasumasa Yamane, Ryo Tokumaru, Hiromi Sawai
  • Patent number: 10236390
    Abstract: A semiconductor device having stable electrical characteristics is provided. Alternatively, a highly reliable semiconductor device suitable for miniaturization or high integration is provided. The semiconductor device includes a first barrier layer, a second barrier layer, a third barrier layer, a transistor including an oxide, an insulator, and a conductor. The insulator includes an oxygen-excess region. The insulator and the oxide are between the first barrier layer and the second barrier layer. The conductor is in an opening of the first barrier layer, an opening of the second barrier layer, and an opening of the insulator with the third barrier layer positioned therebetween.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasumasa Yamane, Motomu Kurata, Ryota Hodo, Takahisa Ishiyama
  • Publication number: 20190035937
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 31, 2019
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Tetsuhiro TANAKA, Hirokazu WATANABE, Yuhei SATO, Yasumasa YAMANE, Daisuke MATSUBAYASHI
  • Patent number: 10192990
    Abstract: A transistor which includes an oxide semiconductor and is capable of high-speed operation and a method of manufacturing the transistor. In addition, a highly reliable semiconductor device including the transistor and a method of manufacturing the semiconductor device. The semiconductor device includes an oxide semiconductor layer including a channel formation region, and a source and drain regions which are provided so that the channel formation region is interposed therebetween and have lower resistance than the channel formation region. The channel formation region and the source and drain regions each include a crystalline region.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: January 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomokazu Yokoi, Yasumasa Yamane
  • Publication number: 20180342601
    Abstract: To provide a semiconductor device including an oxide semiconductor layer with high and stable electrical characteristics, the semiconductor device is manufactured by forming a first insulating layer, forming oxide over the first insulating layer and then removing the oxide n times (n is a natural number), forming an oxide semiconductor layer over the first insulating layer, forming a second insulating layer over the oxide semiconductor layer, and forming a conductive layer over the second insulating layer. Alternatively, the semiconductor device is manufactured by forming the oxide semiconductor layer over the first insulating layer, forming the second insulating layer over the oxide semiconductor layer, forming the oxide over the second insulating layer and then removing the oxide n times (n is a natural number), and forming the conductive layer over the second insulating layer.
    Type: Application
    Filed: July 18, 2018
    Publication date: November 29, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Ryo Tokumaru, Yasumasa Yamane, Akihisa Shimomura, Naoki Okuno
  • Patent number: 10074733
    Abstract: A manufacturing method of a semiconductor device in which the threshold voltage is adjusted is provided. The semiconductor device includes a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the first semiconductor. By performing heat treatment at higher than or equal to 125° C. and lower than or equal to 450° C. and, at the same time, keeping a potential of the gate electrode higher than a potential of the electrode for 1 second or more, the threshold voltage is increased.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: September 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Toshihiko Takeuchi, Yasumasa Yamane, Takayuki Inoue, Shunpei Yamazaki
  • Publication number: 20180233597
    Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 16, 2018
    Inventors: Yoshitaka YAMAMOTO, Tetsuhiro TANAKA, Toshihiko TAKEUCHI, Yasumasa YAMANE, Takayuki INOUE, Shunpei YAMAZAKI
  • Patent number: 10050132
    Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. One feature resides in forming an oxide semiconductor film over an oxygen-introduced insulating film, and then forming the source and drain electrodes with an antioxidant film thereunder. Here, in the antioxidant film, the width of a region overlapping with the source and drain electrodes is longer than the width of a region not overlapping with them. The transistor formed as such has less defects in the channel region, which will improve reliability of the semiconductor device.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: August 14, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yasumasa Yamane, Yuhei Sato, Tetsuhiro Tanaka, Masashi Tsubuku, Toshihiko Takeuchi, Ryo Tokumaru, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toshiya Endo
  • Patent number: 10043913
    Abstract: A semiconductor device with favorable electrical characteristics is provided. In an oxide semiconductor film, a plurality of electron diffraction patterns are observed in such a manner that a surface over which the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm while the position of the film and the position of the electron beam are relatively moved. The electron diffraction patterns include 50 or more electron diffraction patterns observed in different areas. The sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%. The first electron diffraction patterns account for 50% or more. The first electron diffraction pattern includes observation points that are not symmetry or observation points disposed in a circular pattern. The second electron diffraction pattern includes observation points corresponding to the vertices of a hexagon.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: August 7, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Shunpei Yamazaki, Kenichi Okazaki, Chiho Kawanabe
  • Patent number: 10032888
    Abstract: To provide a semiconductor device including an oxide semiconductor layer with high and stable electrical characteristics, the semiconductor device is manufactured by forming a first insulating layer, forming oxide over the first insulating layer and then removing the oxide n times (n is a natural number), forming an oxide semiconductor layer over the first insulating layer, forming a second insulating layer over the oxide semiconductor layer, and forming a conductive layer over the second insulating layer. Alternatively, the semiconductor device is manufactured by forming the oxide semiconductor layer over the first insulating layer, forming the second insulating layer over the oxide semiconductor layer, forming the oxide over the second insulating layer and then removing the oxide n times (n is a natural number), and forming the conductive layer over the second insulating layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Ryo Tokumaru, Yasumasa Yamane, Akihisa Shimomura, Naoki Okuno
  • Patent number: 10032928
    Abstract: Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Yasumasa Yamane, Yuhei Sato, Takahisa Ishiyama, Kenichi Okazaki, Chiho Kawanabe, Masashi Oota, Noritaka Ishihara
  • Patent number: 10032918
    Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Ryo Tokumaru, Yasumasa Yamane, Kiyofumi Ogino, Taichi Endo, Hajime Kimura
  • Publication number: 20180151743
    Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 31, 2018
    Inventors: Shunpei YAMAZAKI, Akihisa SHIMOMURA, Yuhei SATO, Yasumasa YAMANE, Yoshitaka YAMAMOTO, Hideomi SUZAWA, Tetsuhiro TANAKA, Yutaka OKAZAKI, Naoki OKUNO, Takahisa ISHIYAMA
  • Publication number: 20180076296
    Abstract: A semiconductor device having stable electrical characteristics is provided. A semiconductor device that can be miniaturized or highly integrated is provided. One embodiment of the present invention includes a transistor including an oxide, a first barrier layer over the transistor, and a second barrier layer in contact with the first barrier layer. The oxide is in contact with an insulator including an excess-oxygen region. The insulator is in contact with the first barrier layer. The first barrier layer has a thickness greater than or equal to 0.5 nm and less than or equal to 1.5 nm. The second barrier layer is thicker than the first barrier layer.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 15, 2018
    Inventors: Yasumasa YAMANE, Ryo TOKUMARU, Hiromi SAWAI
  • Patent number: 9899535
    Abstract: To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a semiconductor device including the transistor, or a durable semiconductor device. The semiconductor device includes a first transistor using silicon, an aluminum oxide film over the first transistor, and a second transistor using an oxide semiconductor over the aluminum oxide film. The oxide semiconductor has a lower hydrogen concentration than silicon.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: February 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsuhiro Tanaka, Hideomi Suzawa, Yasumasa Yamane, Yuhei Sato, Sachiaki Tezuka
  • Publication number: 20180033892
    Abstract: A semiconductor device having stable electrical characteristics is provided. Alternatively, a highly reliable semiconductor device suitable for miniaturization or high integration is provided. The semiconductor device includes a first barrier layer, a second barrier layer, a third barrier layer, a transistor including an oxide, an insulator, and a conductor. The insulator includes an oxygen-excess region. The insulator and the oxide are between the first barrier layer and the second barrier layer. The conductor is in an opening of the first barrier layer, an opening of the second barrier layer, and an opening of the insulator with the third barrier layer positioned therebetween.
    Type: Application
    Filed: July 18, 2017
    Publication date: February 1, 2018
    Inventors: Yasumasa YAMANE, Motomu KURATA, Ryota HODO, Takahisa ISHIYAMA
  • Patent number: 9882059
    Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Yoshitaka Yamamoto, Hideomi Suzawa, Tetsuhiro Tanaka, Yutaka Okazaki, Naoki Okuno, Takahisa Ishiyama
  • Publication number: 20180006124
    Abstract: A semiconductor device includes a first conductor; a first insulator thereover; a first oxide thereover; a second oxide thereover; a second conductor and a third conductor that are separate from each other thereover; a third oxide over the first insulator, the second oxide, the second conductor, and the third conductor; a second insulator thereover; a fourth conductor thereover; and a third insulator over the first insulator, the second insulator, and the fourth conductor. The second oxide includes a region where the energy of the conduction band minimum of an energy band is low and a region where the energy of the conduction band minimum of the energy band is high. The energy of the conduction band minimum of the third oxide is higher than that of the region of the second oxide where the energy of the conduction band minimum is low. Side surfaces of the first oxide and the second oxide are covered with the third oxide.
    Type: Application
    Filed: June 21, 2017
    Publication date: January 4, 2018
    Inventors: Tsutomu MURAKAWA, Toshihiko TAKEUCHI, Hiroki KOMAGATA, Hiromi SAWAI, Yasumasa YAMANE, Shota SAMBONSUGE, Kazuya SUGIMOTO, Shunpei YAMAZAKI
  • Publication number: 20170352746
    Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. Oxygen is introduced into a surface of an insulating film, and then, an oxide semiconductor, a layer which is capable of blocking oxygen, a gate insulating film, and other films which composes a transistor are formed. For at least one of the first gate insulating film and the insulating film, three signals in Electron Spin Resonance Measurement are each observed in a certain range of g-factor. Reducing the sum of the spin densities of the signals will improve reliability of the semiconductor device.
    Type: Application
    Filed: July 31, 2017
    Publication date: December 7, 2017
    Inventors: Shunpei YAMAZAKI, Akihisa SHIMOMURA, Yasumasa YAMANE, Yuhei SATO, Tetsuhiro TANAKA, Masashi TSUBUKU, Toshihiko TAKEUCHI, Ryo TOKUMARU, Mitsuhiro ICHIJO, Satoshi TORIUMI, Takashi OHTSUKI, Toshiya ENDO