Patents by Inventor Yasumori Fukushima

Yasumori Fukushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110006376
    Abstract: The present invention provides a semiconductor device capable of improving subthreshold characteristics of a PMOS transistor that is included in a thinned base layer and bonded to another substrate, a production method of such a semiconductor device, and a display device. The semiconductor device of the present invention is a semiconductor device, including: a substrate; and a device part bonded to the substrate, the device part including a base layer and a PMOS transistor, the PMOS transistor including a first electrical conduction path and a first gate electrode, the first electrical conduction path being provided inside the base layer on a side where the first gate electrode is disposed.
    Type: Application
    Filed: March 3, 2009
    Publication date: January 13, 2011
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Masao Moriguchi, Kenshi Tada, Steven Roy Droes
  • Publication number: 20100295105
    Abstract: A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.
    Type: Application
    Filed: September 25, 2008
    Publication date: November 25, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Kazuhide Tomiyasu, Yutaka Takafuji, Kenshi Tada, Michiko Takei
  • Publication number: 20100289037
    Abstract: The present invention provides a semiconductor device having a plurality of MOS transistors with controllable threshold values in the same face and easy to manufacture, a manufacturing method thereof and a display device. The invention is a semiconductor device having a plurality of MOS transistors in the same face each having a structure formed by stacking a semiconductor active layer, a gate insulator, and a gate electrode, wherein the semiconductor device includes: an insulating layer stacked on a side opposite to a gate electrode side of the semiconductor active layer; and a conductive electrode stacked on a side opposite to a semiconductor active layer side of the insulating layer and extending over at least two of the plurality of MOS transistors.
    Type: Application
    Filed: October 10, 2008
    Publication date: November 18, 2010
    Inventors: Shin Matsumoto, Yutaka Takafuji, Yasumori Fukushima, kenshi Tada
  • Publication number: 20100283104
    Abstract: An element portion forming step includes an insulating film forming step of forming an insulating film on a surface of a base layer, a conductive layer forming step of uniformly forming a conductive layer on a surface of the insulating film, and an electrode forming step of patterning the conductive layer to form an electrode. A delamination layer forming step of ion implanting a delamination material into the base layer to form a delamination layer is performed before the electrode forming step.
    Type: Application
    Filed: November 25, 2008
    Publication date: November 11, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto
  • Publication number: 20100283103
    Abstract: A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film.
    Type: Application
    Filed: November 14, 2008
    Publication date: November 11, 2010
    Inventors: Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Masao Moriguchi, Yutaka Takafuji
  • Patent number: 7829400
    Abstract: In fabricating a semiconductor device, an element forming surface formation step of forming a plurality of element forming surfaces of different heights on a semiconductor layer to have different levels, a semiconductor element formation step of forming a plurality of semiconductor elements and, one in each of a corresponding number of regions of the semiconductor layer, each region including an associated one of the plurality of element forming surfaces, a level-difference compensation insulating film formation step of forming a level-difference compensation insulating film on the semiconductor layer to cover the semiconductor elements and have a surface with different levels along the element forming surfaces, a release layer formation step of forming a release layer in the semiconductor layer by ion-implanting a peeling material through the level-difference compensation insulating film into the semiconductor layer, and a separation step of separating part of the semiconductor layer along the release layer
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: November 9, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Masao Moriguchi
  • Publication number: 20100270618
    Abstract: The present invention provides a production method of a semiconductor device, capable of improving surface flatness of a semiconductor chip formed on a semiconductor substrate and thereby suppressing a variation in electrical characteristics of the semiconductor chip transferred onto a substrate with an insulating surface, and further capable of improving production yield.
    Type: Application
    Filed: October 14, 2008
    Publication date: October 28, 2010
    Inventors: Michiko Takei, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Steven Roy Droes
  • Publication number: 20100270658
    Abstract: A method is disclosed for producing a semiconductor device produced by (i) doping hydrogen ions or rare gas ions into a device substrate in which a transfer layer (16) is formed, (ii) then bonding the device substrate to a carrier target substrate, and (iii) transferring the transfer layer (16) onto the carrier substrate (30) by cleaving the device substrate along a portion in which the hydrogen ions or the rare gas ions are doped, the method including providing a blocking layer (11) for blocking diffusion of a bubble-causing substance between (i) a bonding surface (13), which serves as a bonding interface between the device substrate and the carrier substrate, and (ii) the transfer layer (16). This prevents bubbles from forming at the bonding interface between the semiconductor substrate and the target substrate due to the diffusion of the bubble-causing substance.
    Type: Application
    Filed: September 12, 2008
    Publication date: October 28, 2010
    Inventors: Kazuo Nakagawa, Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Shin Matsumoto, Kenshi Tada, Yutaka Takafuji
  • Publication number: 20100252885
    Abstract: A semiconductor device (10) is formed by bonding a semiconductor substrate (1) including a CMOS transistor (3) to a glass substrate (2). The semiconductor substrate (1) is formed by partial separation at a separation layer. A P-type high concentration impurity region (39n) is formed in electric connection with a channel region (35n) of an NMOS transistor (3n) so that an electric potential of the channel region (35n) is fixed. The P-type high concentration impurity region (39n) has the same P conductive type as that of the channel region (35n) and also has a concentration higher than that of the channel region (35n). An N-type high concentration impurity region (39p) is formed in electric connection with a channel region (35p) of a PMOS transistor (3p) so that an electric potential of the channel region (35p) is fixed. The N-type high concentration impurity region (39p) has the same N conductive type as that of the channel region (35p) and also has a concentration higher than that of the channel region (35p).
    Type: Application
    Filed: September 19, 2008
    Publication date: October 7, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Kenshi Tada
  • Publication number: 20100252906
    Abstract: A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a second step of bonding the peripheral device unit directly to the substrate, and a third step of forming the thin film device unit on the substrate to which the peripheral device unit is bonded.
    Type: Application
    Filed: July 24, 2008
    Publication date: October 7, 2010
    Inventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kazuo Nakagawa
  • Publication number: 20100244136
    Abstract: The present invention provides a semiconductor device, a single-crystal semiconductor thin film-including substrate, and production methods thereof, each allowing single-crystal semiconductor thin film-including single-crystal semiconductor elements produced by being transferred onto a low heat resistant insulating substrate to have enhanced transistor characteristics and a reduced wiring resistance. The present invention is a production method of a semiconductor device including single-crystal semiconductor thin film-including single-crystal semiconductor elements on an insulating substrate, the production method including a heat treatment step of subjecting a single-crystal semiconductor thin film to a heat treatment at 650° C. or higher, the single-crystal semiconductor thin film including at least part of each one of single-crystal semiconductor elements and boded to an intermediate substrate with a heat-resistant temperature higher than that of the insulating substrate.
    Type: Application
    Filed: October 22, 2008
    Publication date: September 30, 2010
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Kazuo Nakagawa, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei
  • Publication number: 20100244185
    Abstract: The present invention provides a semiconductor device, a single-crystal semiconductor thin film-including substrate, and production methods thereof, each allowing single-crystal semiconductor thin film-including single-crystal semiconductor elements produced by being transferred onto a low heat resistant insulating substrate to have enhanced transistor characteristics. The present invention is a production method of a semiconductor device including single-crystal semiconductor thin film-including single-crystal semiconductor elements on an insulating substrate, the production method including the successive steps of a first heat treatment step and a second heat treatment step, wherein in the first heat treatment step, a single-crystal semiconductor thin film undergoes a heat treatment at lower than 650° C.
    Type: Application
    Filed: October 22, 2008
    Publication date: September 30, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yutaka Takafuji, Yasumori Fukushima, Kenshi Tada, Kazuo Nakagawa, Shin Matsumoto, Kazuhide Tomiyasu
  • Publication number: 20100207212
    Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.
    Type: Application
    Filed: October 21, 2008
    Publication date: August 19, 2010
    Inventors: Michiko Takei, Shin Matsumoto, Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20100155905
    Abstract: A device portion forming step includes an assisting layer forming step of forming a planarization assisting layer, which covers a plurality of conductive films, over a first planarizing layer before forming a second planarizing layer. In the assisting layer forming step, the planarization assisting layer is formed so that a height of the planarization assisting layer from a surface of the first planarizing layer located on a side opposite to the substrate layer becomes equal between at least a part of a region where the conductive films are formed, and at least a part of a region where no conductive film is formed.
    Type: Application
    Filed: April 1, 2008
    Publication date: June 24, 2010
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Kazuhide Tomiyasu, Michiko Takei, Steven Droes
  • Publication number: 20100148261
    Abstract: A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.
    Type: Application
    Filed: October 13, 2006
    Publication date: June 17, 2010
    Inventors: Yasumori Fukushima, Yutaka Takafuji, Michiko Takei, Kazuhide Tomiyasu
  • Publication number: 20100059892
    Abstract: The present invention provides a production method of a semiconductor device, a production method of a display device, a semiconductor device, a production method of a semiconductor element, and a semiconductor element, each capable of providing a lower-resistance semiconductor element which is more finely prepared through more simple steps. The production method of the semiconductor device of the present invention is a production method of a semiconductor device including a semiconductor element on a substrate, wherein the production method includes a metal silicide-forming step of: transferring the semiconductor element onto the substrate, the semiconductor element having a multilayer structure of a silicon layer and a metal layer, and by heating, forming metal silicide from silicon for a metal layer-side part of the silicon layer and metal for a silicon layer-side part of the metal layer.
    Type: Application
    Filed: December 14, 2007
    Publication date: March 11, 2010
    Inventors: Michiko Takei, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji, Masao Moriguchi, Steven Roy Droes
  • Patent number: 7563693
    Abstract: A method for manufacturing a semiconductor substrate comprises the steps of: forming a gate oxide film as an insulating layer on the surface of a semiconductor substrate; implanting boron ions for inhibiting the migration of a peeling substance in the semiconductor substrate to form an anti-diffusion layer in the semiconductor substrate; activating boron in the anti-diffusion layer by heat treatment; implanting hydrogen ions into the semiconductor substrate to form a peel layer in part of the semiconductor substrate at a side of the anti-diffusion layer opposite to the gate oxide film; bonding a glass substrate to the surface of the semiconductor substrate where the gate oxide film has been formed; and heat-treating the semiconductor substrate to separate part of the semiconductor substrate along the peel layer.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: July 21, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Yutaka Takafuji
  • Patent number: 7528446
    Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: May 5, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Yasumori Fukushima, Masao Moriguchi
  • Publication number: 20090001504
    Abstract: A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting substrate is heat-treated at high heat so as to repair crystal defects generated in a transistor channel of the monocrystalline Si wafer when transferring the transistor. The transistor is then made into a chip and transferred onto a TFT substrate. In order to transfer the transistor which has been once separated from the monocrystalline Si wafer, a different method from a stripping method utilizing ion doping is employed.
    Type: Application
    Filed: December 13, 2006
    Publication date: January 1, 2009
    Inventors: Michiko Takei, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20080318390
    Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 25, 2008
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Masao Moriguchi, Yutaka Takafuji