Abstract: The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.

Abstract: A data transmission system which allows received data to be decoded and reproduced in real time by simple decoding and which allows signal reproduction and recording by highly reliable error-correcting decoding, wherein a transmitter encodes transmission data by an error-correcting code enabling control of the error-correcting characteristic and the real-time characteristic at the receiving side and transmits it through a transmission line and a receiver 2a demodulates the received data by a demodulation circuit 102, decodes it by a simple decoding circuit 104 and simultaneously stores it in a storage circuit 110, demultiplexes the decoded data 105a by a demultiplexing circuit 106, and reproduces it by a reproduction circuit 123 in a form for viewing and listening by a user.

Abstract: A wireless relay system (1) comprises a wireless camera (11) and a reception relay station (12). The reception relay station (12) comprises a plurality of external reception units (13) arranged at spatially different positions and an internal reception unit (14). Each reception section (16) in the internal reception unit (14) demodulates a signal received in the external reception unit (13) and outputs a transport stream. At this time, each reception section (16) sets an error indicator flag to 1 for a TS packet causing a transmission error which exceeds the error correction capability. A TS synthesizer section (17) in the internal reception unit (14) completely synchronizes a plurality of input transport streams by referencing synchronization bytes, PID, and CC values, and selects to output a TS packet having the error indicator flag not set to 1.

Abstract: A radio relay system (1) comprises a wireless camera (11) and a signal receiving relay station (12). The wireless camera (11) wirelessly transmits signals to the signal receiving relay station (12) by using the OFDM modulation method. The wireless camera (11) and the signal receiving relay station (12) perform energy dispersion at the time of transmission-line-coding/decoding a transport stream. The PRBS seed (initial value) to be used for the energy dispersion can be externally modified and the user can arbitrarily select a value for the seed.

Abstract: A signal processing apparatus and method and a provision medium arranged to enable detection of a unique pattern in a short time with high accuracy. A value representing a correlation between an input signal and a reference signal is calculated and the calculated correlation value is compared with a predetermined threshold value. The invention makes it possible to detect, for example, a unique word in a short time with high accuracy without influence of noise.

Abstract: An intermediate frequency signal of an OFDM signal received by a tuner (2) is multiplied by a carrier wave by a multiplier (3) and a multiplier (4) to thereby generate an OFDM signal in a base band. The OFDM signal in the base band is FFT processed by an FFT circuit (5) and a resultant signal is outputted to a dividing circuit (10) and a pilot signal extracting circuit (8) in an equalizing circuit (13). A pilot signal extracted by the pilot signal extracting circuit (8) is supplied to an interpolating filter (9) and subjected to an interpolating process. An amplitude component and a phase component in the pilot signal are supplied to the dividing circuit (10). The dividing circuit (10) divides the signal input from the FFT circuit (5) by the amplitude and phase supplied from the interpolating filter (9) and a resultant signal is output to a demapping circuit (11).

Abstract: The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.

Abstract: The time required for switch the channel can be remarkably curtailed. When broadcasting signals through a plurality of information channels with an OFDM system, the plurality of information channels are multiplexed in the sense of frequency and collectively subjected to IFFT modulation for connected transmission instead of subjecting the plurality of information channels independently to OFDM modulation for transmission. With this arrangement, the efficiency of exploitation of frequencies is improved. According to the invention, the OFDM frames are synchronized for each information channel for the purpose of connected transmission. Then, the OFDM receiver can switch the information channel for signal reception, maintaining the frame synchronizing signals.

Abstract: A reception apparatus for OFDM signals having a short initial rise time since start of reception until outputting the sound and/or a picture. An OFDM reception apparatus 1 of the ISDB-T standard presets the TMCC information at the outset in a memory 19 in association with each broadcasting station. This TMCC information contains the information on the RF frequency and the guard interval length, time interleaving pattern information, the information on the carrier modulation scheme and the information on the code rate of the convolutional code. When a user selects a broadcasting station, a control circuit 18 reads out the TMCC information associated with the broadcasting station from the memory 19. The control circuit 18 affords the read-out TMCC information to each circuit to set e.g., the guard interval or the carrier modulation scheme.

Abstract: A calculating apparatus performs FFT calculation or IFFT calculation on input data and then outputs the calculated data. An input buffer memory temporarily stores the input data and outputs it to a memory. An output buffer memory temporarily stores the final data of the calculating apparatus and then outputs it to an external source. The input buffer memory or the output buffer memory is provided with an address generating circuit. The address generating circuit sets the write addresses or the read addresses of the data to be stored in either buffer memory in a predetermined order. Thus, the frequency domain of the data in the calculating apparatus is converted without requiring the use of an external circuit.

Abstract: Butterfly calculations of a cardinal number of four and butterfly calculations of a cardinal number of two are performed by using the same circuitry. When butterfly calculations of a cardinal number of two are performed, predetermined lines in the circuitry are removed by using selectors. Moreover, the multiplication factors of the signal lines which join predetermined complex multiplication circuits with predetermined complex addition circuits are changed from −j to −1, from −1 to 1, from −1 to 1, and from −j to −1. As a result, a pair of butterfly calculating circuit systems (A and B) are formed. On the other hand, when calculations of a cardinal number of four are performed, all the signal lines in the circuitry are connected, and the predetermined multiplication factors of the respective paths are set. As a consequence, a single butterfly calculating circuit system having a cardinal number of four is formed.

Abstract: An apparatus and method for receiving an OFDM signal arranged to accurately reproduce a clock signal. I channel data and Q channel data are differential-demodulated by a differential demodulation circuit and are supplied to a ROM. The ROM reads out an intersymbol phase change amount corresponding to the differential-demodulated data and supplies it to a gate circuit. The gate circuit extracts only a component corresponding to each of pilot signals in the input data, and supplies the extracted component to a sign inversion circuit and to a selector. The selector selects the output from the gate circuit if the pilot signal is a positive frequency value or the output from the sign inversion circuit if the pilot signal is a negative frequency value, and supplies the obtained value to a cumulative addition circuit. The cumulative addition circuit performs cumulative addition of values output from the selector over a symbol period, and outputs the addition result to an average circuit.

Abstract: Frame synchronizing signals held by a synchronization register are Reed-Solomon-coded by a Reed-Solomon coding circuit, then interleaved by an interleave circuit, then convolutional-coded by a convolutional coding circuit, then mapped by a mapping circuit, and then outputted. Thus, the frame synchronizing signals can be stably and quickly detected.

Abstract: A computation apparatus such as a Fast Fourier Transform (FFT) apparatus which processes ordered sets of data in a computation unit (4, 24) operating according to a high-speed clock includes an input buffer (1, 21) arranged to accept data in synchronism with a relatively low-speed clock, and an output buffer (6, 26) arranged to discharge the data in synchronism with the low-speed clock. The apparatus includes an internal memory (3, 23) as well as means such as selectors (2, 22) and (5, 25) for transferring data in synchronism with the high-speed clock from the input buffer to the computation unit or the memory; between the computation unit and the memory; and from the computation unit or the memory to the output buffer. The transferring means is arranged to reorder the data, preferably in reverse-digit sequence, during transfer from the input buffer or during transfer to the output buffer. This avoids the need for a separate reordering memory at the input end or output end of the device.

Abstract: A method for recycling a heat exchanger includes spreading the outer periphery of a metal pipe of a heat exchanger in a predetermined direction, and placing the heat exchanger in the rotary space of a crushing roll which rotates around the axis thereof while slanting at a predetermined angle in order to separate the heat exchanger to the metal pipe and radiating metal fins. The crushing apparatus is provided with a crushing assembly which incorporates a processing space extending at a downward slant at a predetermined angle, an inlet, and a crushing roll applied to the heat exchanger which is rotated about the axis thereof in the processing space and moving down the same.

Abstract: An apparatus and method for receiving an OFDM signal arranged to reproduce correct carriers. I channel data and Q channel data decomposed into subcarrier components by FFT processing are differential-demodulated by a differential demodulation circuit to remove an FFT window phase error and a reproducing carrier phase error. In a differential demodulation circuit, a reproducing carrier frequency error and a phase error dependent on a reproducing clock frequency error are removed and only I-axis data is thereafter output to be stored in a RAM with respect each symbol. A pilot signal selecting data generation circuit supplies the RAM with data which is prepared by suitably shifting pilot signal selecting data used as a reference. Resulting Data read out is accumulated by cumulative addition performed by a cumulative addition circuit.

Abstract: The present invention is used for example digital television broadcasting and provides a good television picture and sound where the signal level is large on the reception side and provides a television picture and sound of a certain degree of quality even in a case where the signal level is small. The signal transmitting apparatus (10) divides the series of input information in accordance with the significance of the content of the data to obtain a plurality of input signals, encodes the input signals with respectively different encoding rates, multiplexes the same at the time slots for transmission, modulates the same by multi-value modulation methods different for every time slot corresponding to the coded signals, and transmits the resultant data via the communication transmission line (20) such as a satellite communication channel to the signal receiving apparatus (30).

Abstract: In order to carry out FFT operations at a high speed, a configuration is adopted where, while a FFT (fast Fourier transform) operation or inverse FFT (inverse fast Fourier transform) operation is being carried out by performing a prescribed number of butterfly operations with the output of a butterfly operator being fed-back to the input of the butterfly operator, at least one of: a first storage part for storing data inputted to the butterfly operator; a second storage part for temporarily storing data outputted from the butterfly operator and feeding-back read-out data to an input of the butterfly operator; and a third storage part, for storing data that has undergone a butterfly operation a prescribed number of times, has a storage part, with the storage part comprising a plurality of divided storage parts.

Abstract: A data reception apparatus receiving a transmission signal that has been modulated by a predetermined modulation method such as a trellis coding, inserted with a predetermined reference data in a predetermined period, and transmitted through a transmission path, and that decodes the received signal. The data reception apparatus includes: a demodulating unit for demodulating the received signal and providing a demodulated signal; a reference data extracting unit for extracting the inserted reference data from the demodulated signal; an estimating unit for estimating the transmission characteristic of the transmission path with reference to the extracted reference data for providing an estimated data; and a decoding unit for decoding the demodulated signal with reference to the estimated data.

Abstract: A Fourier transform arithmetic unit is reduced in cost and size by reducing the number of delay circuits. Data corresponding to each of input symbols is successively divided into quarters by a distribution switch. The first-quarter data is delayed by a delay circuit three times, that is, delayed by a total of 3N/4 (N: the number of data items of one symbol). The second-quarter data is delayed by a second delay circuit two times, that is, delayed by a total of N/2. The third-quarter data is delayed by N/4 by a third delay circuit. The fourth-quarter data is not delayed. These quarters of the input data are supplied to first to fourth input terminals of a butterfly operation device simultaneously with each other, data items in each quarter being input one after another. The butterfly operation device performs the butterfly operation using the data and outputs the operation result.