Abstract: A Fourier transform arithmetic unit which is reduced in cost and size by simplifying the configuration of a butterfly operation device. Data corresponding to each of the unit symbols is divided into first-half data and second-half data by a distribution switch. The first-half data is supplied to a delay circuit to be delayed by N/2. The data delayed by this delay circuit is again supplied to this delay circuit. The second-half data is supplied to another delay circuit to be delayed by N/2. The delayed data is again supplied to this delay circuit to be delayed. In this manner, the first-half data and the second-half data are supplied two times to the input terminals of the butterfly operation device. The butterfly operation device performs one of two butterfly operations (addition) at the time of the first input and performs the other butterfly operation (subtraction) at the time of the second input. That is, the butterfly operation device performs the butterfly operations in a time division manner.

Abstract: In an orthogonal function generating circuit, orthogonal functions are generated with high precision by a small-scale circuit. The circuit uses an orthogonal transformation between time domain digital data and frequency domain digital data to obtain one of the time domain digital data and the frequency domain digital data from the other digital data. The circuit has a first data holder for holding first data and a second data holder for holding second data. A first multiplier multiplies the first data, and a second multiplier multiplies the first data by a second coefficient. A third multiplier multiplies the second data by a third coefficient, and afourth multiplier multiplies the second data by a fourth coefficient.

Abstract: In view of regenerating clock with higher accuracy even under the condition that frequency distortion is generated due to the frequency selective Rayleigh fading, the OFDM (Orthogonal Frequency Division Multiplexing) modulated signal is converted to the baseband OFDM signal in the multipliers and a phase difference between the phase of the carrier forming the OFDM signal and the phase of the carrier before one OFDM symbol is calculated in the differential decoding circuit. A phase error of the carrier is calculated on the basis of the phase difference of the carrier in the carrier regenerating circuit or clock regenerating circuit and the local oscillator to generate the carrier and the local oscillator to generate clock are respectively controlled on the basis of the phase error of a plurality of carriers among those forming the OFDM signal.

Abstract: In a Viterbi decoder and a Viterbi decoding method, a modulating method and a phase of a carrier wave, employed in a transmitter apparatus can be automatically followed up in a receiver apparatus.

Abstract: A transmission system for transmitting information series such as hierarchically coded image data etc. includes at least one transmission apparatus and receiving apparatus. The transmission apparatus has an encoder and a multiplexor. The encoder takes a plurality of information series from a single information source as input, utilizes convolutional coding to code the plurality of inputted information series, and carries out code processing in such a manner that at least one of the plurality of inputted information series is coded with a code rate differing from that of the remaining information series. The higher the priority of the information series, the lower the code rate of the encoding. The multiplexor multiplexes a plurality of convolutional code series outputted from the encoder. The transmission apparatus modulates and transmits an output from the multiplexor. The receiving apparatus has a demultiplexor and a decoder.

Abstract: An orthogonal frequency division multiplex (OFDM) modulation apparatus which can transmit just one of single side bands by a simple circuit and an OFDM demodulation apparatus superior in the ratio of the signal power to noise power ratio, wherein a serial/parallel converter converts the input signal from the serial to parallel format, inputs the results to the 1 to N-1 stage of an inverse discrete Fourier transformation (IDFT) circuit, and inputs a fixed value to the other stages (0 stage and N stage to 2N-1 stage). The IDFT circuit is a 2N input IDFT circuit which performs IDFT processing on the input signal converted to the parallel format by the serial/parallel converter and inputs the real number portion of the transformation result to a parallel/serial converter and the imaginary number portion to a parallel/serial converter. The imaginary number portion of the output signal of the IDFT circuit becomes the Hilbert transformation of the real number portion.

Abstract: An orthogonal frequency division multiplex (OFDM) demodulation apparatus which accurately reproduces a clock and accurately generates a time window for discrete Fourier transformation (DFT) for stable demodulation of an OFDM modulated signal, wherein a clock reproduction circuit of the OFDM demodulation apparatus includes a Costas computation circuit and processes a signal corresponding to the specific carrier wave signal of a predetermined single wave for each symbol out of the I and Q channel signals obtained by subjecting the OFDM modulated signal to DFT to generate a control voltage using the Costas computation circuit and low pass filters and operates a voltage control oscillator to reproduce a clock signal. The clock signal is divided to produce the time window signals used in the DFT circuit.

Abstract: When an orthogonal frequency division multiplex (OFDM) modulated signal is demodulated by discrete Fourier transformation (DFT), DFT is performed using a time window of an accurate phase synchronized with the synchronization symbol. Therefore, first, the reproduction clock is divided to generate a basic time window signal. The results of the DFT processing on the OFDM signal are used to detect the phase deviation and the phase of the basic time window signal is adjusted based on that phase deviation. Preferably, the results of DFT are used for synchronization pull-in to generate a stable time window signal. More preferably a DFT circuit for demodulating the OFDM modulated signal and a DFT circuit for generating a time window signal are provided separately.

Abstract: A variable length coder includes a buffer memory for temporarily storing data, to be coded, a coding table for producing a variable length code and a code length thereof in response to the data supplied from the buffer memory, a shifter for shifting the variable length code according to a shift control signal, registers for storing shifted data supplied from the shifter through a gate, and a multiplexer for selectively feeding high-order or low-order bits of the data stored in the registers to the gate, and a register for accumulating code lengths from the coding table. The buffer memory, the coding table, the shifter, and the multiplexer are controlled by output data from the register.

Abstract: A television receiver in which a video signal of an interlaced system is received and converted in field frequency by using field memories (6a) and (6b) and then fed to a picture receiving tube (9). In this case, the picture receiving tube (9) is subjected to a vertical deflection scanning by a vertical synchronizing signal of a constant period and the video signal in each field of the video signal to be supplied to the picture receiving tube (9) is delayed by a predetermined time by controlling, for example, the read-out timings of the field memories (6a) and (6b) to thereby keep an interlace-ratio constant. Consequently, since the respective vertical cycles are equal to one another, even if the parabolic current wave of the vertical cycle for deflection correcting, for example, is superposed on the horizontal deflecting current, the horizontal deflection current waveform is equal in each vertical period so that the jitter can be prevented from being produced at the right and left ends of the picture screen.

Abstract: In accordance with the present invention, a read clock frequency applied to field memories (16a) and (16b) comprising a converting circuit (16) which converts the field frequency of a video signal is changed at the unit of a vertical cycle whereby vertical cycles of video signals read out from the field memories (16a) and (16b) are made substantially equal to one another. Accordingly, a horizontal deflecting current waveform on which a parabolic wave current of, for example, the vertical cycle is superposed becomes equal during each vertical period so that it becomes possible to prevent a jitter from being produced at right and left ends of a picture screen.

Abstract: A television receiver having a signal input terminal supplied with an interlace video signal and a signal coverter connected to the input terminal for converting the interlace video signal to a non-interlace signal to be displayed. The signal converter includes a signal inserting circuit for inserting new line signals between two successive line signals of the interlace signal, the new line signals being formed by interpolating one of the preceding and succeeding line signals in the interlace signal. A three dimensional filter is connected to the signal converter for attentuating vertical and horizontal high frequency components in the non-interlace video signal only when the non-interlace signal includes both of the vertical and horizontal high frequency components.

Abstract: A double-scanning non-interlace television receiver with a vertical aperture correction circuit for receiving an interlace television signal having alternating odd and even fields of scanned lines which are interlaced, as displayed, comprises a receiver circuit which receives the interlace television signal and which generates interlace scanning line signals for each of the fields, a visual display apparatus, a non-interlace converting circuit which converts the interlace scanning line signals for each of the fields to non-interlace scanning line signals which are displayed on the visual display apparatus, with each of the scanned lines being scanned twice, and a high frequency emphasizing circuit which emphasizes the high frequency components of the interlace scanning line signals.

Abstract: A double-scanning non-interlace color television receiver which receives an interlace color television signal having alternating odd and even fields of scanned lines which are normally interlaced, as displayed, comprises a receiver circuit which receives the interlace color television signal and includes a circuit which generates respective chroma and luminance scanning line signals in response thereto, a visual display apparatus, and a non-interlace converting circuit with a luminance double-scanning circuit which generates an averaged luminance scanning line signal from each two consecutive luminance scanning line signals of the same field, and which supplies the consecutive luminance scanning line signals and the averaged luminance scanning line signal to the visual display apparatus for display by the latter of each averaged luminance scanning line signal between the respective two consecutive luminance scanning line signals, and a circuit which supplies to the visual display apparatus color difference si

Abstract: A double-scanning non-interlace television receiver for receiving an interlace television signal having alternating odd and even fields of scan lines which are normally interlaced, as displayed, comprises a receiver circuit which receives the interlace television signal and generates received line signals representative of the scan lines of a field being received, a visual display apparatus, and a non-interlace converting circuit connected to the receiver circuit which generates an averaged line signal from two consecutive received line signals and serially supplies the averaged line signal and the consecutive received line signals to the visual display apparatus for display by the latter, with each averaged line signal being supplied and displayed between the respective received line signals.

Abstract: An indicator is responsive to a gain control voltage applied to an amplifier for indicating the gain of the amplifier irrespective of amplitude of the signal being amplified. The amplifier may be an audio amplifier in a television receiver which also contains an electronic tuner tuned by a tuning voltage, in which case, the indicator may alternatively indicate the tuning voltage while a television channel is being preset and the gain of the audio amplifier at other times.