Patents by Inventor Yasunari Umemoto
Yasunari Umemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210234026Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
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Patent number: 11075289Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.Type: GrantFiled: July 29, 2019Date of Patent: July 27, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Takayuki Tsutsui, Satoshi Tanaka
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Publication number: 20210183854Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.Type: ApplicationFiled: March 1, 2021Publication date: June 17, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Shigeki KOYA, Yasunari UMEMOTO, Takayuki TSUTSUI
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Publication number: 20210184022Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.Type: ApplicationFiled: March 1, 2021Publication date: June 17, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Daisuke TOKUDA, Tsunekazu SAIMEI, Hiroaki TOKUYA
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Publication number: 20210126591Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: ApplicationFiled: January 7, 2021Publication date: April 29, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Kenichi NAGURA
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Patent number: 10978579Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.Type: GrantFiled: July 8, 2019Date of Patent: April 13, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
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Publication number: 20210098585Abstract: A collector layer is disposed on a substrate. The collector layer is a continuous region when viewed in plan. A base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. An emitter mesa layer is disposed on the emitter layer. Two base electrodes are located outside the emitter mesa layer and within the base layer when viewed in plan. The two base electrodes are electrically connected to the base layer. Two capacitors are disposed on or above the substrate. Each of the two capacitors is connected between a corresponding one of the two base electrodes and a first line above the substrate. Two resistance elements are disposed on or above the substrate. Each of the two resistance elements is connected between a corresponding one of the two base electrodes and a second line on or above the substrate.Type: ApplicationFiled: September 21, 2020Publication date: April 1, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shaojun MA, Shigeki KOYA
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Patent number: 10964693Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.Type: GrantFiled: June 13, 2019Date of Patent: March 30, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Shigeki Koya, Yasunari Umemoto, Takayuki Tsutsui
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Publication number: 20210091215Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.Type: ApplicationFiled: December 2, 2020Publication date: March 25, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU
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Patent number: 10957617Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.Type: GrantFiled: April 3, 2019Date of Patent: March 23, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Masao Kondo, Isao Obu, Yasunari Umemoto, Yasuhisa Yamamoto, Masahiro Shibata, Takayuki Tsutsui
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Publication number: 20210083080Abstract: An electrically conductive sub-collector layer is provided in a surface layer portion of a substrate. A collector layer, a base layer, and an emitter layer are located within the sub-collector layer when viewed in plan. The collector layer is connected to the sub-collector layer. An emitter electrode and a base electrode are long in a first direction when viewed in plan. The emitter electrode overlaps the emitter layer. The base electrode and the emitter electrode are discretely located away from each other in a second direction orthogonal to the first direction. A collector electrode is located on one side in the second direction with respect to the emitter electrode and is not located on the other side when viewed in plan. A base line is connected to the base electrode in a manner so as to adjoin a portion other than longitudinal ends of the base electrode.Type: ApplicationFiled: August 25, 2020Publication date: March 18, 2021Applicant: Murata Manufacturing Co., Ltd.Inventors: Kenji SASAKI, Yasunari UMEMOTO, Shigeki KOYA, Shinnosuke TAKAHASHI, Masao KONDO
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Publication number: 20210044256Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.Type: ApplicationFiled: October 28, 2020Publication date: February 11, 2021Inventors: Shigeki KOYA, Takayuki TSUTSUI, Yasunari UMEMOTO, Isao OBU, Satoshi TANAKA
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Patent number: 10903803Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.Type: GrantFiled: February 7, 2020Date of Patent: January 26, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Kenichi Nagura
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Patent number: 10886388Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.Type: GrantFiled: March 18, 2020Date of Patent: January 5, 2021Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasunari Umemoto, Shigeki Koya, Isao Obu
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Publication number: 20200402932Abstract: A semiconductor element includes a semiconductor substrate, first and second amplifiers provided on the semiconductor substrate and adjacently provided in a first direction, a first reference potential bump provided on a main surface of the semiconductor substrate, and connecting the first amplifier and a reference potential, a second reference potential bump provided on the main surface, being adjacent to the first reference potential bump in the first direction, and connecting the second amplifier and a reference potential, and a rectangular bump provided on the main surface, provided between the first and second reference potential bumps in a plan view, and formed such that a second width in a second direction orthogonal to the first direction is larger than a first width in the first direction. The second width is larger than a width of at least one of the first and second reference potential bumps in the second direction.Type: ApplicationFiled: June 18, 2020Publication date: December 24, 2020Applicant: Murata Manufacturing Co., Ltd.Inventors: Shigeki KOYA, Yasunari UMEMOTO, Isao OBU, Masao KONDO, Yuichi SAITO, Takayuki TSUTSUI
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Publication number: 20200382083Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Inventors: Isao OBU, Satoshi TANAKA, Takayuki TSUTSUI, Yasunari UMEMOTO
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Patent number: 10855232Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.Type: GrantFiled: November 14, 2018Date of Patent: December 1, 2020Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Shigeki Koya, Takayuki Tsutsui, Yasunari Umemoto, Isao Obu, Satoshi Tanaka
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Publication number: 20200373417Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU
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Publication number: 20200357699Abstract: A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.Type: ApplicationFiled: May 7, 2020Publication date: November 12, 2020Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Isao OBU, Kaoru IDENO
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Publication number: 20200335611Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Applicant: Murata Manufacturing Co., Ltd.Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA