Abstract: An arithmetic processing device includes an instruction decode unit, an instruction execution unit and an instruction hold unit, wherein the instruction hold unit includes; a first holder including a plurality of first entries each configured to hold a decoded instruction; a second holder including a smaller number of second entries than the number of the first entries; a first selector configured to select an instruction to be registered in the second holder from instructions held in the first entries and store identification information that identifies the selected instruction into any of the second entries; and a second selector configured to sequentially select an executable instruction from instructions registered in the second holder, input the selected executable instruction to the instruction execution unit, and detect a dependency between the instruction inputted to the instruction execution unit and the instructions registered in the second holder.

Abstract: A first entry, when outputting an instruction stored in the first entry to a first arithmetic unit and when an execution cycle number of the instruction stored in the first entry is equal to or more than a threshold value, outputs a use inability signal of the first arithmetic unit to a second entry, a reservation station includes a controller configured to, when the use inability signal of the first arithmetic unit is output and then a use inability discontinuation condition is satisfied, perform control to discontinue execution of the first arithmetic unit, store a state of the first arithmetic unit in a storage element, and discontinue output of the use inability signal of the first arithmetic unit, and the second entry, when output of the use inability signal of the first arithmetic unit is discontinued, outputs an instruction stored in the second entry to the first arithmetic unit.

Abstract: An arithmetic processing unit includes, an instruction decoder; three or more operators to, when the instruction is a multi-data instruction, process in parallel the plural data, and when the instruction is a non-multi-data instruction, process the singular data individually; storage destination register groups corresponding to the operators to store operation results from the operators; renaming register groups corresponding respectively to the operators to store the operation results; and a register renaming unit to store an association between a specified storage destination register specified by an instruction and an allocated renaming register.

Abstract: An arithmetic processing device includes: a first instruction execution unit configured to include plural staging latches and execute a first instruction by a pipeline operation requiring only a single clock for transition of data between first plural staging latches including a staging latch at a final stage from among the plural staging latches, and a multi-cycle operation requiring plural clocks for transition of data between second plural staging latches positioning at a previous stage side than the first plural staging latches from among the plural staging latches; a second instruction execution unit configured to execute a second instruction; and an instruction control unit configured to input the first instruction and the second instruction, issue the first instruction to the first instruction execution unit and issue the second instruction to the second instruction execution unit such that the execution of the first instruction and the second instruction are partly overlapped.

Abstract: A processing device has: a plurality of registers configured to correspond to a plurality of accessible register windows; and an instruction decoder configured to inhibit, when, during an execution of a first instruction of changing a number of a current register window by one, a second instruction of changing the number of the current register window by one in a direction same as a direction of the first instruction is input, a decode of the second instruction until when the execution of the first instruction is completed, and to perform, when, during the execution of the first instruction of changing the number of the current register window by one, a second instruction of changing the number of the current register window by one in a direction opposite to the direction of the first instruction is input, a decode of the second instruction during the execution of the first instruction.

Abstract: A calculation-processing-device includes: a decoder unit including, a first-counter to increment a first-count-value and to decrement the-first-count-value, and a second-counter configured to increment a second-count-value and to decrement the second-count-value; a first-instruction-executing-unit to execute an instruction of the first-class; a second-instruction-executing-unit to execute an instruction of the-second class; a first-instruction holding unit including a plurality of first-entries, to input the instruction of the first-class held in one of the plurality of first-entries into the first-instruction-executing-unit; a second-instruction-holding-unit including a plurality of second-entries, to input the instruction of the second-class held in one of the plurality of second-entries into the second-instruction-executing-unit; and first-control-unit to output the second-release-notification, and to change the output timing of the second-release-notification when a predetermined relationship is establish

Abstract: A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction immediately following two instructions of the second prefix instruction, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruc

Abstract: A data processing device includes a plurality of entries and a plurality of output ports, allocates the plurality of entries to a plurality of arbitration groups corresponding to the plurality of output ports respectively when a clock is inputted thereto, arbitrates the output ports for each of the allocated arbitration groups when data held in the entry is outputted from the output port, and outputs data held in the entry according to an arbitration result.

Abstract: A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.

Abstract: Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit, and the other is used to store the result of a processing operation performed on second data by another processing unit. Those stored processing results are then transferred to result registers. Normal data processing instructions, on the other hand, instruct a processing operation on third data. When a normal data processing instruction is decoded, one allocatable register is selected and used to store the result of processing that a processing unit performs on the third data. The stored processing result is then transferred to a result register.

Abstract: An arithmetic processing unit includes a cache memory, a register configured to hold data used for arithmetic processing, a correcting controller configured to detect an error in data retrieved from the register, a cache controller configured to access a cache area of a memory space via the cache memory or a noncache area of the memory space without using the cache memory in response to an instruction executing request for executing a requested instruction, and notify a report indicating that the requested instruction is a memory access instruction for accessing the noncache area, and an instruction executing controller configured to delay execution of other instructions subjected to error detection by the correcting controller while the cache controller executes the memory access instruction for accessing the noncache area when the instruction executing controller receives the notified report.

Abstract: A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.

Abstract: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. And the instruction execution control device has a thread selection circuit (30) which detects a state where an instruction has not been completed for a predetermined period during simultaneous multi-thread operation, and controls such that all the reservation stations (5, 6 and 7) can execute only a predetermined thread. Therefore if an entry that cannot be executed from the reservation stations (5, 6 and 7) exists, execution of an entry in the thread that cannot be executed can be enabled by stopping the execution of the thread which has been executed continuously.

Abstract: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.

Abstract: Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit, and the other is used to store the result of a processing operation performed on second data by another processing unit. Those stored processing results are then transferred to result registers. Normal data processing instructions, on the other hand, instruct a processing operation on third data. When a normal data processing instruction is decoded, one allocatable register is selected and used to store the result of processing that a processing unit performs on the third data. The stored processing result is then transferred to a result register.

Abstract: A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction after two instructions written to the second area respectively, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction gene

Abstract: A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.

Abstract: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.

Abstract: In a system that executes a program by simultaneously running a plurality of threads, the entries in a CSE 17 are divided into groups of the number of threads. Each group allocates continuous storage areas, and holds the initial position of the entry in each group as a pointer in a point register selection circuit 35. The pointer is associated with each thread. A thread selection circuit 36 selects one thread for determining an execution completion of an instruction, allows an entry selection circuit 37 to store a copy of the entry of the thread from the CSE 17 in the completion target entry 38, allows a completion determination unit 39 to perform a completion determination and update programmable resources. A thread is selected without a bias toward one thread.

Abstract: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. And the instruction execution control device has a thread selection circuit (30) which detects a state where an instruction has not been completed for a predetermined period during simultaneous multi-thread operation, and controls such that all the reservation stations (5, 6 and 7) can execute only a predetermined thread. Therefore if an entry that cannot be executed from the reservation stations (5, 6 and 7) exists, execution of an entry in the thread that cannot be executed can be enabled by stopping the execution of the thread which has been executed continuously.