Abstract: A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register.

Abstract: A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops a program and interrupts a verification, the execution of the command retry is suppressed by assuming that no parity error is detected.

Abstract: An instruction execution apparatus comprising a register storing a copy of contents of a maximum number of entries that are executable simultaneously in one cycle with the entry storing the oldest unreleased instruction at a head among all entries in an instruction storage device after execution of the instructions, a completion condition determination section 44 for determining whether the instructions stored in the entries of the register are completed in the cycle for determining completion conditions of the entries in the instruction storage device, and an entry release section 44 for releasing only the entries that are determined to be completed by the completion condition determination section among all entries in the instruction storage device, which allows the entries in the CSE to be released smoothly even though the number of entries in a commitment stack entry, or clock frequency, is increased.

Abstract: A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops a program and interrupts a verification, the execution of the command retry is suppressed by assuming that no parity error is detected.

Abstract: An instruction execution apparatus comprising a register 43 for storing a copy of contents of the maximum number of entries that are executable simultaneously in one cycle with the entry storing the oldest unreleased instruction at the head among all entries in an instruction storage device 42 after execution of the instructions, a completion condition determination section 44 for determining whether the instructions stored in the entries of the register are completed in the cycle for determining completion conditions of the entries in the instruction storage device, and an entry release section 45 for releasing only the entries that are determined to be completed by the completion condition determination section among all entries in the instruction storage device, which allows the entries in the CSE to be released smoothly even though the number of entries in the CSE, or clock frequency, is increased.