Patents by Inventor Yasunori Inoue

Yasunori Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070131985
    Abstract: A semiconductor device and a method for manufacturing the same are provided, in which the work function of a gate electrode being in contact with a gate insulating film can be efficiently adjusted while depletion of the gate electrode is suppressed. An SOI substrate is composed of a p-type silicon substrate, a buried oxide film, and a single crystal silicon layer. Furthermore, source and drain regions are provided in the single crystal silicon layer. In the single crystal silicon layer, the surface between the source and drain regions serves as a channel layer. A gate insulating film is formed on the single crystal silicon layer (the channel layer). On the gate insulating film is provided a polysilicon gate electrode composed of metal particles of TiN and a polysilicon film. The metal particles of TiN include particles being in contact with the gate insulating film and particles being out of contact with this film.
    Type: Application
    Filed: November 29, 2006
    Publication date: June 14, 2007
    Inventors: Kazunori Fujita, Yoshikazu Yamaoka, Satoru Shimada, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20070120203
    Abstract: A semiconductor device includes a semiconductor substrate on which a source region and a drain region are formed, an insulating film formed on the semiconductor substrate and interposed between the source region and the drain region, a gate electrode formed on the insulating film, metal-bearing particles formed on the interface between the insulation film and the gate electrode, and an insulator which has been changed from a part of metal-bearing particles protruding from an edge of the interface.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 31, 2007
    Inventors: Yoshikazu Yamaoka, Kazunori Fujita, Satoru Shimada, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20070023202
    Abstract: A circuit board and a circuit apparatus using the same which can prevent displacement and film exfoliation ascribable to thermal expansion, and suppress a drop in reliability at increasing temperatures. The circuit board of the circuit apparatus includes a metal substrate having pierced holes as a core member. Protrusions are formed on the top ends of the pierced holes, and depressions are formed in the bottom ends of the pierced holes. Wiring pattern layers are formed on both sides of this metal substrate via respective insulating layers. In order to establish electrical connection between the wiring pattern layers, a conductor layer which connects the wiring pattern layers is formed through the metal substrate via the pierced holes. The conductor layer thereby establishes electrical conduction between the wiring pattern layers. Furthermore, a semiconductor chip is directly connected to the surface side of the circuit board via solder balls.
    Type: Application
    Filed: July 28, 2006
    Publication date: February 1, 2007
    Inventors: Kiyoshi Shibata, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20060267189
    Abstract: A circuit device of the present invention includes a first element which is placed parallel to a first reference plane and which senses a physical quantity, and a second element placed parallel to a second reference plane which intersects the first reference plane at a predetermined angle. The circuit device further includes a sealing resin for integrally sealing the first and second elements, a first conductive pattern which is electrically connected to the first element and placed parallel to the first reference plane and which has a back surface exposed from the sealing resin, and a second conductive pattern which is electrically connected to the second element and placed parallel to the second reference plane and which has a back surface exposed from the sealing resin.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 30, 2006
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20060252232
    Abstract: A circuit device of preferred embodiments of the present invention includes: a circuit element with electrodes formed in a peripheral part thereof; connecting portions connected to surfaces of the electrodes; and redistribution lines which are continuous to the respective connecting portions and extended in parallel to the main surface of the circuit element. In preferred embodiments of the present invention, the connecting portions and the redistribution lines are integrally formed of one piece of metal. Accordingly, there is no place where different materials are connected in a portion between the connecting portions and the redistribution lines, thus improving a joint reliability of the entire device against a thermal stress or the like.
    Type: Application
    Filed: April 24, 2006
    Publication date: November 9, 2006
    Inventors: Ryosuke Usui, Yasunori Inoue, Hideki Mizuhara
  • Publication number: 20060238961
    Abstract: The ground noise is reduced which propagates between circuit elements in a circuit device having a multiple stack structure. A grounding bonding pad provided on the surface of a second circuit element is connected to a bonding wire provided on the surface of a conduction layer via a grounding wire such as gold. A bonding pad provided on the surface of the conductive layer is connected to a lead provided on a ground wire via a grounding wire such as gold. This structure creates a capacitance between the second circuit element and the conduction layer so as to prevent the propagation of noise circuit from element to the ground wiring.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 26, 2006
    Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai, Yasunori Inoue
  • Publication number: 20060219432
    Abstract: A circuit device capable of suppressing reduction of reliability resulting from heat generated in a circuit element is obtained. This circuit device comprises a first insulating layer having a first opening and a second opening, a first conductor filling up the first opening of the first insulating layer, a second conductor, formed along the inner side surface of the second opening of the first insulating layer, having a concave upper surface and a circuit element arranged above a region of the first insulating layer formed with the first opening.
    Type: Application
    Filed: March 30, 2006
    Publication date: October 5, 2006
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Katsunori Kobayashi
  • Publication number: 20060199371
    Abstract: A semiconductor device includes a substrate and wirings located on the substrate. A passivation film including a first insulating film containing an impurity is located on the wirings. The first insulating film is formed from silicon oxide film materials containing greater than one percent carbon.
    Type: Application
    Filed: May 19, 2006
    Publication date: September 7, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Hideki Mizuhara, Yasunori Inoue, Hiroyuki Watanabe, Masaki Hirase, Kaori Misawa, Hiroyuki Aoe, Kimihide Saito, Hiroyasu Ishihara
  • Publication number: 20060191894
    Abstract: In a heat radiation structure for an electronic appliance in which heat generated in a heat generating member inside a flap of the electronic appliance is radiated to a space outside the flap, a heat radiation plate integrally formed with a circuit element is thermally coupled to the heat generating member and is exposed outside the flap. Heat generated in the heat generating member is conducted to the heat radiation plate via a contact portion and is radiated to a space outside the flap from an exposed surface along with heat generated in the circuit element.
    Type: Application
    Filed: February 27, 2006
    Publication date: August 31, 2006
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Noriaki Kojima, Hiroyuki Watanabe, Shinya Nakano
  • Publication number: 20060193108
    Abstract: A thin circuit device that can operate at a high speed is provided. The circuit device includes a first circuit element and a circuit element portion formed on a substrate. The first circuit element and the circuit element portion are arranged in such a manner that element surfaces thereof are opposed to each other. A terminal formed on the element surface of the first circuit element and a terminal formed on the element surface of the circuit element portion are electrically connected to each other via conductive particles in a binder forming an anisotropic conductive film and a via. The anisotropic conductive film and a third insulating resin film are bonded by thermocompression bonding in the same step, thereby simplifying manufacturing steps of the circuit device.
    Type: Application
    Filed: February 23, 2006
    Publication date: August 31, 2006
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Makoto Murai
  • Publication number: 20060158804
    Abstract: Multiple semiconductor device components and passive device components fixed to a substrate are embedded within an electroconductive-film/insulating-resin-film structure, and are thermally bonded to an insulating resin film.
    Type: Application
    Filed: March 9, 2006
    Publication date: July 20, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Ryosuke Usui, Yasunori Inoue
  • Publication number: 20060131746
    Abstract: A circuit device in which highly reliable sealing with a resin can be achieved is provided. A semiconductor chip is provided on one surface of an insulating resin film and a conductive layer that is electrically connected to the semiconductor chip is provided on another surface of the insulating resin film. A solder ball (electrode) for the connection to a circuit board is provided on the conductive layer. An insulating resin layer is further provided between the conductive layer and the circuit board to embed the electrode therein. In this manner, the circuit device is formed. A side face of the semiconductor chip is covered with the insulating resin film.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 22, 2006
    Inventors: Yasuhiro Kohara, Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20060049995
    Abstract: An integrated antenna type circuit apparatus which provides excellent circuit characteristics while suppressing an increase in packaging area. The integrated antenna type circuit apparatus includes an insulating base, a semiconductor circuit device, chip parts, a molding resin, an antenna conductor, a ground conductor, and external lead electrodes. The plurality of chip parts are mounted on the insulating base, and are soldered to electrodes of wiring conductors on the top of the insulating base for electric and physical connection. The insulating base has a multilayer structure, being formed by laminating a plurality of insulator layers. The antenna conductor is formed on the bottom of the insulating base. A wiring conductor adjacent to the antenna conductor is provided with the ground conductor so that it overlaps with the antenna conductor.
    Type: Application
    Filed: August 31, 2005
    Publication date: March 9, 2006
    Inventors: Toshikazu Imaoka, Sawai Tetsuro, Atsushi Sakai, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20060012028
    Abstract: A device mounting board on which a device is mounted is provided with a substrate and an insulating film provided on one surface of the substrate. The substrate and the insulating film include glass fiber impregnated with epoxy resin. The epoxy resin impregnation ratio of the glass fiber included in the insulating resin film is higher than that of the glass fiber included in the substrate.
    Type: Application
    Filed: June 7, 2005
    Publication date: January 19, 2006
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Yusuke Igarashi, Takeshi Nakamura
  • Publication number: 20060001166
    Abstract: A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected to the second wiring layer in a desired position through a connecting portion formed so as to penetrate the first insulating layer. The connecting portion includes a first connecting portion protruding in a thickness direction from the first wiring layer, and a second connecting portion protruding in the thickness direction from the second wiring layer. The first connecting portion and the second connecting portion contact each other at an intermediate portion in the thickness direction of the insulating layer.
    Type: Application
    Filed: June 24, 2005
    Publication date: January 5, 2006
    Inventors: Yusuke Igarashi, Takeshi Nakamura, Yasunori Inoue, Ryosuke Usui, Hideki Mizuhara
  • Publication number: 20050285147
    Abstract: Circuit elements including a plurality of semiconductor devices and passive elements embedded in an insulating resin film are formed on a metal substrate having a surface roughness Ra of 0.3 to 10 ?m. This produces an anchoring effect occurs between the substrate and the insulating film, thereby improving the adhesiveness between the substrate and the insulating resin film.
    Type: Application
    Filed: June 29, 2005
    Publication date: December 29, 2005
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20050272252
    Abstract: Provided is a circuit device capable of inhibiting an insulating layer from separating from a substrate. This circuit device comprises a substrate mainly constituted of metal including a first metal layer having a first thermal expansion coefficient, a second metal layer, formed on the first metal layer, having a second thermal expansion coefficient different from the first thermal expansion coefficient of the first metal layer and a third metal layer, formed on the second metal layer, having a third thermal expansion coefficient different from the second thermal expansion coefficient of the second metal layer, an insulating layer formed on the substrate, a conductive layer formed on the insulating layer and a circuit element electrically connected to the conductive layer.
    Type: Application
    Filed: May 27, 2005
    Publication date: December 8, 2005
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Yusuke Igarashi, Takeshi Nakamura
  • Publication number: 20050263911
    Abstract: A circuit device suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, and a manufacturing method thereof are provided. According to a hybrid integrated circuit device of the present invention and a manufacturing method thereof, a first conductive film is laminated on a first insulating layer, and a first wiring layer is formed by patterning the first conductive film. Next, a second conductive film is laminated on a second insulating layer. Thereafter, by partially removing the second insulating layer and the second conductive film in a desired spot, a connection part for connecting the wiring layers to each other is formed.
    Type: Application
    Filed: May 31, 2005
    Publication date: December 1, 2005
    Inventors: Yusuke Igarashi, Takeshi Nakamura, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui
  • Publication number: 20050263846
    Abstract: In a manufacturing method of a hybrid integrated circuit device 10 according to the present invention, a first dummy pattern D1 is provided on a first wiring layer 18A. Furthermore, a second dummy pattern D2 is provided on a second wiring layer 18B. The first dummy pattern D1 and the second dummy pattern D2 are connected through a connection part 25 which penetrates an insulation layer 17. Hence, heat dissipation through a dummy pattern can be actively performed. In addition, even in the cases where a multi-layered wiring is formed, it is possible to provide a circuit device which can secure a heat dissipation property.
    Type: Application
    Filed: May 26, 2005
    Publication date: December 1, 2005
    Inventors: Yasunori Inoue, Ryosuke Usui, Yasuhiro Kohara, Nobuhisa Takakusakai, Takeshi Nakamura
  • Publication number: 20050212091
    Abstract: A via hole is formed by a first step of forming an opening in a resin insulating film by laser radiation, a second step of forming an opening in said resin insulating film by dry etching and a third step of performing reverse sputtering in a plasma environment.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 29, 2005
    Inventors: Ryosuke Usui, Yasunori Inoue, Hideki Mizuhara