Patents by Inventor Yasunori Inoue

Yasunori Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8022533
    Abstract: Circuit elements including a plurality of semiconductor devices and passive elements embedded in an insulating resin film are formed on a metal substrate having a surface roughness Ra of 0.3 to 10 ?m. This produces an anchoring effect occurs between the substrate and the insulating film, thereby improving the adhesiveness between the substrate and the insulating resin film.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 20, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20110193222
    Abstract: A semiconductor module manufacturing method includes a step of bonding a semiconductor wafer, which has a plurality of semiconductor elements each of which has an element electrode formed thereon, on an expansible first insulating resin layer; a step of dicing the semiconductor wafer; a step of expanding the first insulating resin layer to widen a gap between semiconductor elements; a pressure-bonding step of pressure-bonding a metal plate whereupon an electrode is arranged and the semiconductor elements with the widened gaps in between, by having a second insulating resin layer in between, and electrically connecting the electrode and the element electrodes; a step of forming a wiring layer which corresponds to each semiconductor element by selectively removing the metal plate and forming a plurality of semiconductor modules connected by the first insulating resin layer and the second insulating resin layer; and a step of separating the semiconductor modules by cutting the first insulating resin layer and th
    Type: Application
    Filed: March 18, 2009
    Publication date: August 11, 2011
    Inventors: Ryosuke Usui, Yasunori Inoue, Mayumi Nakasato, Katsumi Ito
  • Publication number: 20110180933
    Abstract: A wiring layer is formed on a substrate, and a semiconductor device is mounted on the substrate. The wiring layer and the semiconductor device are sealed by a sealing resin. A conductive member is used to fill a through hole formed in the sealing resin in a predetermined position of the wiring layer and is provided so as to cover over the sealing resin. The metal foil is provided on the upper surface of the conductive member, and the metal foil and the wiring layer are electrically connected via the conductive member.
    Type: Application
    Filed: May 29, 2009
    Publication date: July 28, 2011
    Inventors: Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Kenichi Ezaki, Hironori Nagasaki, Mayumi Nakasato
  • Publication number: 20110158273
    Abstract: A semiconductor laser device includes a Si(100) substrate in which a recess having an opening and a bottom face surrounded by inner wall surfaces is formed, a semiconductor laser element placed on the bottom face, and a translucent sealing glass, mounted on top of the Si(100) substrate, which seals the opening. The laser light emitted from the semiconductor laser element is reflected by a metallic reflective film formed on the inner wall surface and then transmits through the sealing glass so as to be emitted externally.
    Type: Application
    Filed: December 28, 2010
    Publication date: June 30, 2011
    Inventors: Yoshio OKAYAMA, Yasunori Inoue, Takenori Goto, Kazushi Mori, Yuuki Ota, Naoteru Matsubara
  • Publication number: 20110074025
    Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.
    Type: Application
    Filed: December 6, 2010
    Publication date: March 31, 2011
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Yoshio Okayama, Kiyoshi Shibata, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Tetsuya Yamamoto, Masurao Yoshii
  • Publication number: 20110011829
    Abstract: A device mounting board on which a device is mounted is provided with a substrate and an insulating film provided on one surface of the substrate. The substrate and the insulating film include glass fiber impregnated with epoxy resin. The epoxy resin impregnation ratio of the glass fiber included in the insulating resin film is higher than that of the glass fiber included in the substrate.
    Type: Application
    Filed: September 14, 2010
    Publication date: January 20, 2011
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Yusuki Igarashi, Takeshi Nakamura
  • Publication number: 20100323498
    Abstract: A circuit device of preferred embodiments of the present invention includes: a circuit element with electrodes formed in a peripheral part thereof; connecting portions connected to surfaces of the electrodes; and redistribution lines which are continuous to the respective connecting portions and extended in parallel to the main surface of the circuit element. In preferred embodiments of the present invention, the connecting portions and the redistribution lines are integrally formed of one piece of metal. Accordingly, there is no place where different materials are connected in a portion between the connecting portions and the redistribution lines, thus improving a joint reliability of the entire device against a thermal stress or the like.
    Type: Application
    Filed: August 26, 2010
    Publication date: December 23, 2010
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Yasunori Inoue, Hideki Mizuhara
  • Patent number: 7855452
    Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: December 21, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Yoshio Okayama, Kiyoshi Shibata, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Tetsuya Yamamoto, Masurao Yoshii
  • Publication number: 20100288550
    Abstract: There has been such a problem that conventional element mounting substrates and circuit devices using such substrates are not easily thinned, as there is a wiring layer formed on each of the substrates and that a part of the wiring layer is protruded and used as a bump electrode. In an element mounting substrate of this invention and a circuit device using such substrate, a through hole is arranged on an insulating base material, and a wiring layer is protruded from the surface of the insulating base material through the through hole. The protruding section of the wiring layer is used as a bump electrode, and a semiconductor element is mounted on the insulating base material. With such structure, the element mounting substrate is thinned, and the circuit device using such substrate is also thinned.
    Type: Application
    Filed: July 28, 2008
    Publication date: November 18, 2010
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20100264552
    Abstract: A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.
    Type: Application
    Filed: August 8, 2008
    Publication date: October 21, 2010
    Inventors: Mayumi Nakasato, Ryosuke Usui, Yasunori Inoue, Kiyoshi Shibata
  • Patent number: 7808114
    Abstract: A circuit device of preferred embodiments of the present invention includes: a circuit element with electrodes formed in a peripheral part thereof; connecting portions connected to surfaces of the electrodes; and redistribution lines which are continuous to the respective connecting portions and extended in parallel to the main surface of the circuit element. In preferred embodiments of the present invention, the connecting portions and the redistribution lines are integrally formed of one piece of metal. Accordingly, there is no place where different materials are connected in a portion between the connecting portions and the redistribution lines, thus improving a joint reliability of the entire device against a thermal stress or the like.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: October 5, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Yasunori Inoue, Hideki Mizuhara
  • Publication number: 20100244171
    Abstract: A semiconductor module includes a lower wiring substrate having a semiconductor device mounted and an upper wiring substrate having an opening in a position corresponding to the semiconductor device and having a packaging-component mountable region around the opening. The lower wiring substrate and the upper wiring substrate are electrically connected to each other via a plurality of solder balls provided around the semiconductor device. The solder balls are covered with light blocking under-fills.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 30, 2010
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Yasunori Inoue
  • Patent number: 7791120
    Abstract: A manufacturing method of a circuit device that is formed by embedding a circuit in an insulating film is provided, the method including pressure bonding by a vacuum adhesion method on a first film a film that contains an insulating film between elements and is provided with a recess or a penetrated portion to adhere a second film 160 that constitutes a recess 190; embedding a pasty material of an element constituent member inside of the recess 190 by squeegeeing means such as a squeegee; and applying treatment such as drying to the material to form embedding members such as a high resistance member that becomes a resistor 180 and a high dielectric constant member 170 that constitutes a capacitor.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: September 7, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Yasunori Inoue
  • Patent number: 7768132
    Abstract: A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected to the second wiring layer in a desired position through a connecting portion formed so as to penetrate the first insulating layer. The connecting portion includes a first connecting portion protruding in a thickness direction from the first wiring layer, and a second connecting portion protruding in the thickness direction from the second wiring layer. The first connecting portion and the second connecting portion contact each other at an intermediate portion in the thickness direction of the insulating layer.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: August 3, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Takeshi Nakamura, Yasunori Inoue, Ryosuke Usul, Hideki Mizuhara
  • Publication number: 20100166958
    Abstract: Object To provide a technique for efficiently forming a metal oxide thin film made of zinc oxide or the like on a substrate at a low cost, without requiring a large amount of electrical energy. Means of Solution H2 gas and O2 gas or, H2O2 gas, is introduced into a catalytic reactor to make contact with a catalyst to generate H2O gas, and the H2O gas is jetted from the catalytic reactor to react with a metal compound gas, to thereby deposit a metal oxide thin film on a substrate and fabricate the metal oxide thin film.
    Type: Application
    Filed: May 16, 2008
    Publication date: July 1, 2010
    Applicants: National University Corporation Nagaoka University of Technology, Tokyo Electron Limited
    Inventors: Kanji Yasui, Hiroshi Nishiyama, Masatoshi Tsukichi, Yasunori Inoue, Masasuke Takata
  • Publication number: 20100139088
    Abstract: A circuit board and a circuit apparatus using the same which can prevent displacement and film exfoliation ascribable to thermal expansion, and suppress a drop in reliability at increasing temperatures. The circuit board of the circuit apparatus includes a metal substrate having pierced holes as a core member. Protrusions are formed on the top ends of the pierced holes, and depressions are formed in the bottom ends of the pierced holes. Wiring pattern layers are formed on both sides of this metal substrate via respective insulating layers. In order to establish electrical connection between the wiring pattern layers, a conductor layer which connects the wiring pattern layers is formed through the metal substrate via the pierced holes. The conductor layer thereby establishes electrical conduction between the wiring pattern layers. Furthermore, a semiconductor chip is directly connected to the surface side of the circuit board via solder balls.
    Type: Application
    Filed: February 9, 2010
    Publication date: June 10, 2010
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Kiyoshi SHIBATA, Ryosuke Usui, Yasunori Inoue
  • Patent number: 7724536
    Abstract: A circuit device capable of suppressing reduction of reliability resulting from heat generated in a circuit element is obtained. This circuit device comprises a first insulating layer having a first opening and a second opening, a first conductor filling up the first opening of the first insulating layer, a second conductor, formed along the inner side surface of the second opening of the first insulating layer, having a concave upper surface and a circuit element arranged above a region of the first insulating layer formed with the first opening.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: May 25, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Katsunori Kobayashi
  • Publication number: 20100112760
    Abstract: Multiple semiconductor device components and passive device components fixed to a substrate are embedded within an electroconductive-film/insulating-resin-film structure, and are thermally bonded to an insulating resin film.
    Type: Application
    Filed: October 21, 2009
    Publication date: May 6, 2010
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Ryosuke USUI, Yasunori Inoue
  • Patent number: 7700383
    Abstract: A manufacturing method for a semiconductor device comprises: mounting a semiconductor element, having an alignment mark, on a substrate; forming a composite of metal film and insulating film such that the surface of the semiconductor element is covered therewith; and removing a part of the composite of metal film and insulating film so as to expose the alignment mark. The position of each electrode of the semiconductor element mounted on the substrate is determined based upon detection results obtained by detection of the exposed alignment mark.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: April 20, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Yasunori Inoue
  • Patent number: 7683266
    Abstract: A circuit board and a circuit apparatus using the same which can prevent displacement and film exfoliation ascribable to thermal expansion, and suppress a drop in reliability at increasing temperatures. The circuit board of the circuit apparatus includes a metal substrate having pierced holes as a core member. Protrusions are formed on the top ends of the pierced holes, and depressions are formed in the bottom ends of the pierced holes. Wiring pattern layers are formed on both sides of this metal substrate via respective insulating layers. In order to establish electrical connection between the wiring pattern layers, a conductor layer which connects the wiring pattern layers is formed through the metal substrate via the pierced holes. The conductor layer thereby establishes electrical conduction between the wiring pattern layers. Furthermore, a semiconductor chip is directly connected to the surface side of the circuit board via solder balls.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 23, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kiyoshi Shibata, Ryosuke Usui, Yasunori Inoue