Patents by Inventor Yasunori Inoue

Yasunori Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090321119
    Abstract: A device mounting board is provided with: a substrate structural unit including a substrate made of a composition containing amorphous silicon, a first adhesive layer provided on one of the main surfaces of the substrate, and a second adhesive layer provided on the other main surface of the substrate; a first wiring layer provided on the main surface of the first adhesive layer on the opposite side from the substrate; a second wiring layer provided on the main surface of the second adhesive layer on the opposite side from the substrate; and a via conductor, which is provided in a via hole that penetrates the substrate, the first adhesive layer, and the second adhesive layer, which electrically connects the first wiring layer and the second wiring layer.
    Type: Application
    Filed: June 30, 2009
    Publication date: December 31, 2009
    Inventors: Yasuhiro Kohara, Ryosuke Usui, Yasunori Inoue
  • Patent number: 7622805
    Abstract: Multiple semiconductor device components and passive device components fixed to a substrate are embedded within an electroconductive-film/insulating-resin-film structure, and are thermally bonded to an insulating resin film.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: November 24, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Yasunori Inoue
  • Patent number: 7615856
    Abstract: An integrated antenna type circuit apparatus which provides excellent circuit characteristics while suppressing an increase in packaging area. The integrated antenna type circuit apparatus includes an insulating base, a semiconductor circuit device, chip parts, a molding resin, an antenna conductor, a ground conductor, and external lead electrodes. The plurality of chip parts are mounted on the insulating base, and are soldered to electrodes of wiring conductors on the top of the insulating base for electric and physical connection. The insulating base has a multilayer structure, being formed by laminating a plurality of insulator layers. The antenna conductor is formed on the bottom of the insulating base. A wiring conductor adjacent to the antenna conductor is provided with the ground conductor so that it overlaps with the antenna conductor.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: November 10, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsushi Sakai, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20090250251
    Abstract: In a circuit device where a wiring layer, an insulating resin and a circuit element are stacked together in such a manner as to embed a bump structure into the insulating resin, the connection reliability between the bump structure and the circuit element is enhanced. A circuit device (10) has a structure where a wiring layer (20), an insulating resin layer (30) and a circuit element (40) are stacked in this order by a pressure bonding. The wiring layer (20) is provided with bump electrodes (22) in positions that correspond respectively to element electrodes of a circuit element (40). The insulating resin layer (30) is formed of a material that develops plastic flow when pressurized. The bump electrode (22) penetrates the insulating resin layer (30) and is electrically connected to a corresponding element electrode (42).
    Type: Application
    Filed: November 30, 2006
    Publication date: October 8, 2009
    Inventors: Kiyoshi Shibata, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20090183906
    Abstract: A substrate for mounting a device includes: an insulating resin layer made of an insulating resin; a wiring layer provided on one major surface of the insulating resin layer; and a projected portion that projects toward the direction opposite to the insulating resin layer from the wiring layer, and that is used for supporting a low-melting metal ball, while being connected to the wiring layer electrically. The wiring layer and the projected portion are formed into one body.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 23, 2009
    Inventors: Hajime KOBAYASHI, Yasuyuki Yanase, Yoshio Okayama, Yasunori Inoue
  • Patent number: 7553164
    Abstract: A circuit device of the present invention includes a first element which is placed parallel to a first reference plane and which senses a physical quantity, and a second element placed parallel to a second reference plane which intersects the first reference plane at a predetermined angle. The circuit device further includes a sealing resin for integrally sealing the first and second elements, a first conductive pattern which is electrically connected to the first element and placed parallel to the first reference plane and which has a back surface exposed from the sealing resin, and a second conductive pattern which is electrically connected to the second element and placed parallel to the second reference plane and which has a back surface exposed from the sealing resin.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: June 30, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
  • Patent number: 7507658
    Abstract: A via hole is formed by a first step of forming an opening in a resin insulating film by laser radiation, a second step of forming an opening in said resin insulating film by dry etching and a third step of performing reverse sputtering in a plasma environment.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: March 24, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Yasunori Inoue, Hideki Mizuhara
  • Publication number: 20090057903
    Abstract: Cost is suppressed and a semiconductor module is made thinner. The semiconductor is of a structure where a semiconductor element is embedded in a recess formed in a wiring substrate. A substrate electrode provided around the recess and an element electrode are electrically connected through a wiring formed integrally with bumps.
    Type: Application
    Filed: March 28, 2008
    Publication date: March 5, 2009
    Inventors: Yoshio OKAYAMA, Yasunori INOUE, Ryosuke USUI
  • Patent number: 7492045
    Abstract: Connection reliability in electrode portions of a semiconductor module is improved. A semiconductor wafer is prepared where a plurality of semiconductor substrates each having an electrode and a protective film at the surface is formed in a matrix shape. Next, at the surface of the semiconductor wafer (semiconductor substrate) a insulation layer is held between the semiconductor substrate and a copper sheet (metal sheet) formed integrally with a bump containing a plastic region on a tip part. With the insulating held between them, the semiconductor substrate, the insulating layer and the copper sheet are press-formed by a press machine into a single block. The bump penetrates the insulating layer, and the plastic region on the tip part is plastic deformed at a contact surface with an electrode, so that the bump and the electrode are electrically connected together.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 17, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshio Okayama, Ryosuke Usui, Yasunori Inoue
  • Patent number: 7453153
    Abstract: The ground noise is reduced which propagates between circuit elements in a circuit device having a multiple stack structure. A grounding bonding pad provided on the surface of a second circuit element is connected to a bonding wire provided on the surface of a conduction layer via a grounding wire such as gold. A bonding pad provided on the surface of the conductive layer is connected to a lead provided on a ground wire via a grounding wire such as gold. This structure creates a capacitance between the second circuit element and the conduction layer so as to prevent the propagation of noise circuit from element to the ground wiring.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: November 18, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsushi Saita, Toshikazu Imaoka, Tetsuro Sawai, Yasunori Inoue
  • Patent number: 7439614
    Abstract: In a manufacturing method of a hybrid integrated circuit device 10 according to the present invention, a first dummy pattern D1 is provided on a first wiring layer 18A. Furthermore, a second dummy pattern D2 is provided on a second wiring layer 18B. The first dummy pattern D1 and the second dummy pattern D2 are connected through a connection part 25 which penetrates an insulation layer 17. Hence, heat dissipation through a dummy pattern can be actively performed. In addition, even in the cases where a multi-layered wiring is formed, it is possible to provide a circuit device which can secure a heat dissipation property.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: October 21, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasunori Inoue, Ryosuke Usul, Yasuhiro Kohara, Nobuhisa Takakusaki, Takeshi Nakamura
  • Publication number: 20080217769
    Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.
    Type: Application
    Filed: January 30, 2008
    Publication date: September 11, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Yoshio Okayama, Kiyoshi Shibata, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Tetsuya Yamamoto, Masurao Yoshii
  • Publication number: 20080197482
    Abstract: A semiconductor module is provided, which is capable of suppressing the deterioration of reliability and improving heat radiation. The semiconductor module includes: a semiconductor substrate in which electrodes of a circuit element are formed on its surface; a re-wiring pattern connected to the electrodes to ensure large pitch of the electrodes; an electrode integrally formed with the re-wiring pattern; an insulating layer formed on a rear surface of the semiconductor substrate; a radiator formed on the insulating layer; and projections integrally formed with the radiator and penetrating the insulating layer to connect to the rear surface of the semiconductor substrate.
    Type: Application
    Filed: July 27, 2007
    Publication date: August 21, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Masayuki Nagamatsu, Ryosuke Usui, Yasunori Inoue
  • Publication number: 20080128903
    Abstract: Connection reliability in electrode portions of a semiconductor module is improved. A semiconductor wafer is prepared where a plurality of semiconductor substrates each having an electrode and a protective film at the surface is formed in a matrix shape. Next, at the surface of the semiconductor wafer (semiconductor substrate) a insulation layer is held between the semiconductor substrate and a copper sheet (metal sheet) formed integrally with a bump containing a plastic region on a tip part. With the insulating held between them, the semiconductor substrate, the insulating layer and the copper sheet are press-formed by a press machine into a single block. The bump penetrates the insulating layer, and the plastic region on the tip part is plastic deformed at a contact surface with an electrode, so that the bump and the electrode are electrically connected together.
    Type: Application
    Filed: October 30, 2007
    Publication date: June 5, 2008
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Yoshio Okayama, Ryosuke Usui, Yasunori Inoue
  • Patent number: 7315083
    Abstract: A circuit device suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, and a manufacturing method thereof are provided. According to a hybrid integrated circuit device of the present invention and a manufacturing method thereof, a first conductive film is laminated on a first insulating layer, and a first wiring layer is formed by patterning the first conductive film. Next, a second conductive film is laminated on a second insulating layer. Thereafter, by partially removing the second insulating layer and the second conductive film in a desired spot, a connection part for connecting the wiring layers to each other is formed.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: January 1, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Takeshi Nakamura, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui
  • Publication number: 20070235812
    Abstract: A semiconductor device operating at low voltage is provided where a threshold voltage is controlled with ease. A semiconductor substrate is element-isolated by element isolation regions. A source region and a source region are spaced from each other on the semiconductor substrate. A gate electrode is formed between the source region and the drain by way of a gate insulator. A plurality of insulating particles are embedded in the gate electrode in a scattered manner at an interface between the gate insulator and the gate electrode, where the particles are in contact with the gate insulator.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 11, 2007
    Inventors: Hideaki Fujiwara, Kazunori Fujita, Yoshikazu Yamaoka, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20070176303
    Abstract: A highly reliable circuit device is provided at low cost. The circuit device includes a semiconductor element electrically connected to a wiring layer (copper plate and plating film) and passive parts sealed by a molded resin layer. The wiring layer has a predetermined pattern formed by a conductive member. The molded resin layer has projections protruding from gaps in the adjacent wiring layer toward an underside of the wiring layer. Thereby, the drop of yield is prevented and the highly reliable circuit device is provided at low cost.
    Type: Application
    Filed: December 27, 2006
    Publication date: August 2, 2007
    Inventors: Makoto Murai, Ryosuke Usui, Tetsuro Sawai, Toshikazu Imaoka, Yasunori Inoue
  • Publication number: 20070164349
    Abstract: A circuit board includes a substrate and an insulating layer. The substrate has a first surface. The insulating layer has a second surface and is connected to the substrate. The first surface is in contact with the second surface. Heat-conductive particles are provided in the insulating layer. A part of the particles projects from the second surface of the insulating layer and is in contact with the first surface of the substrate.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 19, 2007
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Mayumi Nakasato, Makoto Murai, Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20070131985
    Abstract: A semiconductor device and a method for manufacturing the same are provided, in which the work function of a gate electrode being in contact with a gate insulating film can be efficiently adjusted while depletion of the gate electrode is suppressed. An SOI substrate is composed of a p-type silicon substrate, a buried oxide film, and a single crystal silicon layer. Furthermore, source and drain regions are provided in the single crystal silicon layer. In the single crystal silicon layer, the surface between the source and drain regions serves as a channel layer. A gate insulating film is formed on the single crystal silicon layer (the channel layer). On the gate insulating film is provided a polysilicon gate electrode composed of metal particles of TiN and a polysilicon film. The metal particles of TiN include particles being in contact with the gate insulating film and particles being out of contact with this film.
    Type: Application
    Filed: November 29, 2006
    Publication date: June 14, 2007
    Inventors: Kazunori Fujita, Yoshikazu Yamaoka, Satoru Shimada, Hideki Mizuhara, Yasunori Inoue
  • Publication number: 20070120203
    Abstract: A semiconductor device includes a semiconductor substrate on which a source region and a drain region are formed, an insulating film formed on the semiconductor substrate and interposed between the source region and the drain region, a gate electrode formed on the insulating film, metal-bearing particles formed on the interface between the insulation film and the gate electrode, and an insulator which has been changed from a part of metal-bearing particles protruding from an edge of the interface.
    Type: Application
    Filed: November 27, 2006
    Publication date: May 31, 2007
    Inventors: Yoshikazu Yamaoka, Kazunori Fujita, Satoru Shimada, Hideki Mizuhara, Yasunori Inoue