Abstract: A mounting structure of a semiconductor package can improve resistance against thermal and mechanical external force. The mounting structure of a semiconductor package establishes electrical connection of a pad on a printing circuit board to a connection wiring by soldering the semiconductor package. The pad may be integrally formed with a via. The soldering may be performed by penetrating a part of solder within the via so that the connection wiring is connected to the pad through the via at a layer different from a layer of the pad.

Abstract: An image output apparatus and a camera each include a light source for illuminating an image recorded on a developed film drawn out from a loaded cartridge containing the developed film, an image reading device for reading information of the image through photoelectric conversion, and an image information output device for displaying the information of the image on an image display device. The image reading device is a two-dimensional photoelectric conversion device, which has a size approximately equal to or larger than a size of an image area on the developed film, is disposed in the proximity of the developed film, and receives light beams carrying the information of the image that have passed through the developed film or have passed through the developed film and imaged through an imaging lens system.

Abstract: A structure for mounting a SAW (Surface Acoustic Wave) device includes photosensitive resin filling a gap between the SAW device and a mounting substrate in the peripheral portion of the SAW device. The entire structure is substantially as small in size as the SAW device and light weight. The photosensitive resin is formed in a region including pads for connection in order to absorb thermal stresses and extraneous forces apt to act on the pads. Second resin may surround the photosensitive resin or may be provided in a laminate structure together with the photosensitive resin so as to enhance a sealing ability. A method of mounting a SAW device is also disclosed.

Abstract: In order to detect a base station for a call connect or handover in almost real time while a mobile communication apparatus is moving, the measured base station selecting unit 110 refers to the measured base station table 101 and selects a next base station to be measured. The measuring unit 111 measures the signal quality for the selected base station. The measuring result judging unit 112 compares the measured signal quality with a predetermined threshold and judges whether the measurement of the signal quality of the present base station should be continued or whether a switch to measuring a next base station should be performed. The periphery base station table updating unit 113 rearranges the content of the periphery base station table 102 in descending order of signal quality, based on the information stored in the periphery base station table 102 and on the averages of the signal quality measurements.

Abstract: A semiconductor device comprises a substrate on which a plurality of external connection terminals are formed, and a semiconductor chip provided with a plurality of connection terminals. The connection terminals are connected to corresponding external connection terminals by electrical wiring. Each of predetermined connection terminals in the connection terminals of the semiconductor chip is connected to two or more corresponding external connection terminals on the substrate. Preferably, 90% or more of the connection terminals of the semiconductor chip are connected to two or more corresponding external connection terminals. When the semiconductor device is installed on a circuit board, the semiconductor device is mounted on the circuit board with its external connection terminals facing the circuit board, and electric connections between the semiconductor device and the circuit board is established by the external connection terminals.

Abstract: A chip package device comprises on its outside surface a plurality of wire bonding electrodes adjacent a plurality of facedown electrodes. The chip package device comprises an IC chip having a plurality of chip electrodes on its face surface and a contact sheet having an inside surface on the face surface and comprising on the outside surface a plurality of conductor patterns which comprises portions extending through the contact sheet to the chip electrodes, respectively, and defines the facedown and the wire bonding electrodes. Such chip package devices can be mounted on a printed circuit board in whichever of a facedown and a wire bonding manner when primary and secondary pads are formed on the board for mechanical and electrical connection to the facedown electrodes, respectively, and for electric connection by bonding wires to the wire bonding electrodes, respectively.

Abstract: A semiconductor output circuit serves as an interface circuit between LSIs having a high and a low supply voltages. The output circuit has at least a pre-buffer and an output stage circuit. The output stage circuit has a pull-up n-channel transistor arranged between an output pad and a low-voltage power source. The output pad may receive a high voltage from an external circuit, or the LSI operating with high supply voltage. The pre-buffer applies a voltage in the range of a ground voltage and a high voltage to the gate of the pull-up transistor, to turn on and off the pull-up transistor. The output stage circuit further has a reverse current prevention circuit formed between and connected to the low-voltage power source and the pull-up transistor, to block a reverse current flowing from the output pad to the low-voltage power source when the high voltage is applied to the output pad.

Abstract: A chip package device comprises on its outside surface a plurality of wire bonding electrodes adjacent a plurality of facedown electrodes. The chip package device comprises an IC chip having a plurality of chip electrodes on its face surface and a contact sheet having an inside surface on the face surface and comprising on the outside surface a plurality of conductor patterns which comprises portions extending through the contact sheet to the chip electrodes, respectively, and defines the facedown and the wire bonding electrodes. Such chip package devices can be mounted on a printed circuit board in whichever of a facedown and a wire bonding manner when primary and secondary pads are formed on the board for mechanical and electrical connection to the facedown electrodes, respectively, and for electric connection by bonding wires to the wire bonding electrodes, respectively.

Abstract: A level conversion circuit comprises a first CMOS circuit connected between a high voltage (5 V: VDD) power supply and ground to receive an input signal IN1 having an amplitude between a low voltage (3 V: VCC) and a ground voltage (0 V), a second CMOS circuit connected between the 5 V power supply and ground to output an output signal OUT1 having an amplitude between 5 V and 0 V, and first and second intermediate circuits cross-connected between the first and second CMOS circuits. All MOS transistors constituting these circuits have the gate oxide films whose allowable breakdown voltage is lower than 5 V and higher than 3 V.

Abstract: To an input terminal is connected one end of the source-to-drain current path of an NMOS the gate of which is connected to Vcc. The other end of the current path of the NMOS is connected by a protection circuit comprised of a PMOS and an NMOS to the common gates of a PMOS and an NMOS in the input stage of an internal circuit. In the protection circuit, the PMOS has its source and gate connected to Vcc and its drain connected to the common gates of the PMOS and the NMOS, while the NMOS has its source and gate connected to Vss and its drain connected to the common drains of the PMOS and the NMOS.

Abstract: Disclosed is a method of manufacturing bare chip mounting multi-layer printed circuit board in which arbitrary numbers of wiring circuit conductor layers and insulating layers are alternately stacked on one or both surfaces of a printed circuit board as a substrate, and a recessed portion with an upper opening capable of mounting and resin-encapsulating a bare chip part is formed on the surface of the printed circuit board, wherein at least the uppermost one of the insulating layers is made from a photosensitive resin, and the bare chip part mounting recessed portion is formed by photoetching the insulating layer made from the photosensitive resin. Since the bare chip part mounting recessed portion is formed by photoetching, the recessed portion can be easily and reliably formed. This results in a high product accuracy and allows a packaged part to be freely, additionally mounted even on the recessed portion.

Abstract: An LSI chip is mounted on an LSI board. Sub-buffer circuit areas where input buffers, output buffers or input/output buffers are to be formed are provided in signal lines extending from the pad to the internal circuit of the LSI chip. Each sub-buffer circuit area has a plurality of basic elements, such as transistors and resistors, connected in parallel to one another so that different combinations of those elements can be selected by switches. A latch controller is incorporated in the LSI chip, and it has latch circuits serially connected to form a shift register structure. This latch controller sends a program signal for determining the buffer circuit characteristic to the sub-buffer circuit areas. This program signal is generated when program data is input to the latch controller. The program data is given serially via input buffers from the pads on the LSI chip. The latch controller transfers the program data to the latch circuits one after another in synchronism with a clock signal.

Abstract: In a multi-chip module, a laminate wiring board is formed with stepped recesses. Electrodes to be connected to the electrodes of a bare-chip semiconductor device are subjected to non-electrolytic gold plating. This realizes wire bonding which is as short in distance and as low in loop as possible. To seal each recess with insulating resin, use is made of screen printing using a mesh screen which has a great aperture ratio and a small thickness.

Abstract: The pulse output circuit device comprises two transistors (2, 4) for constructing an output buffer, a transistor (7) connected between the output line (OUTP) of the output buffer and the high potential supply voltage (VDD), a transistor (8) connected between the output line (OUT) of the output buffer and the low potential supply voltage (GND), a control circuit (39) for applying a gate signal to the transistor (7), and a control circuit (40) for applying a gate signal to the transistor (8).

Abstract: There is provided a semiconductor integrated circuit including an output circuit having a first buffer section to which a first power supply voltage is applied and an input signal is supplied to amplify and output the input signal, and a second buffer section to which a second power supply voltage is applied and a signal output from said first buffer section is supplied to amplify and output the signal outside through an output terminal, a switching element which has two terminals respectively connected to said output terminal and a ground voltage terminal and receives a control signal to change a conductive resistance, and a bias circuit for receiving the input signal or a signal output from said first buffer section, generating a control signal, and supplying the control signal to said switching element to control the conductive resistance of said switching element so as not to allow a potential of said output terminal to exceed a predetermined value.

Abstract: A gate array chip is supplied with an operation voltage of 5V. A logic circuit formed of gate arrays in a chip is operated on an operation voltage of 3.3V. The potential of 3.3V is derived by lowering the potential of 5V by use of a voltage lowering circuit disposed in the chip. A level shifter and a converter are disposed in an I/O peripheral circuit to shift the signal level by use of the chip external signal and chip internal signal so that a signal of 5V amplitude can be input or output.

Abstract: In an integrated circuit device using a plurality of different power supply voltages, the application of an input voltage exceeding the power supply voltages to an input/output circuit is prevented. When a p-type substrate is used, a plurality n-wells are formed to surround an integrated circuit region on a central portion of the substrate. When an n-type substrate is used, a plurality of p-wells are formed in the same manner. A predetermined power supply voltage is applied to each well to select transistors of the input/output buffer in accordance with the voltage level of an external voltage.

Abstract: A bipolar transistor/insulated gate transistor hybrid semiconductor device comprises a well region formed on a semiconductor substrate to serve as a first active region of a bipolar transistor, an insulated gate transistor having source and drain regions formed in the well region, which acts as a back gate of the insulated gate transistor, and second and third active regions of the bipolar transistor formed in the well region. At least one of the second and third active regions is used in common to one of the source and drain regions of the insulated gate transistor. A plurality of well regions is regularly arranged to constitute a gate array.

Abstract: A semiconductor integrated circuit includes a current source for supplying a current i, a resistor, a switch having a control end connected to the resistor, an output terminal connected to the output end of the switch, a comparator having a current path which is connected at one end to a connection node between the resistor and the control end of the switch and connected at the other end to the output terminal. The comparator compares a voltage (i.times.R) occurring across the resistor with a potential V of the output terminal and permits the current i to flow into the output terminal when the relation (i.times.R.gtoreq.V) is attained.

Abstract: A CMOS output buffer comprises an output stage circuit including MOS transistors each having a CMOS structure, for outputting a signal, and an output stage control circuit arranged prior to the output stage circuit. The output stage control circuit includes a pull-up circuit and a pull-down circuit for controlling the gate of the final stage MOS transistor of the MOS transistors so that a speed at which a gate-to-source voltage varies when the final stage MOS transistor is turned on, is slower than a speed at which the gate-to-source voltage varies when the final stage MOS transistor is turned off.