Patents by Inventor Yasuo Iijima

Yasuo Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4839792
    Abstract: According to the portable electronic apparatus of the invention, when a data string is to be written in a data memory, information indicating whether the data string is valid or not is appended to the data string, and the data string is stored. When a read instruction is supplied from a portable electronic apparatus handling system, a CPU connected to the data memory appends the information, indicating validity or invalidity of the data string, to the start of the readout data string, and supplies the data string to the portable electronic apparatus handling system. When the data string supplied from the portable electronic apparatus handling system is to be written in the data memory, the CPU appends the information indicating invalidity to the data string and writes the data string, thereby updating the information indicating invalidity to information indicating validity after the completion of the data string writing.
    Type: Grant
    Filed: June 18, 1987
    Date of Patent: June 13, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuo Iijima
  • Patent number: 4833595
    Abstract: The portable electronic apparatus of the invention has a memory for storing externally-supplied data, and a central processing unit (CPU 15) for accessing the memory. The memory is divided into a plurality of areas. Each area has pointer data indicating a final address at which the data is written in that area, and a table that lists start and end addresses of each area. A write instruction to be supplied to the portable electronic apparatus consists of a write function code filed, a write area designating field, a data string length field, and a data string. The CPU refers to the table based on the write area designating field of the supplied write instruction, reads an end address of the designated area and pointer data, and subtracts the pointer data from the end address, thereby calculating a remaining memory capacity which is stored in a data remaining counter.
    Type: Grant
    Filed: September 18, 1987
    Date of Patent: May 23, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuo Iijima
  • Patent number: 4827512
    Abstract: According to a portable medium (IC card) of this invention, a memory area is divided into a system program area and a user program area. A text transmitted between the IC card and a host system connected thereto includes a command text and a response text. The command or response text includes a flag indicating that the text is written in the user program area or the system program area. The memory area has a conversion table for a function code and the start address of a program corresponding to the function code. The conversion table is looked up using the given function code as a parameter, thereby obtaining the start address of the corresponding program. The memory area has a correspondence table between a newly added function code and the start address of an added function program. The added function program is selectively executed.
    Type: Grant
    Filed: October 6, 1986
    Date of Patent: May 2, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhisa Hirokawa, Yasuo Iijima
  • Patent number: 4800520
    Abstract: A portable electronic device of this invention has a control CPU (Central Processing Unit) and a data memory. The data memory is divided into a plurality of areas, and each area consists of a data area and an attribute area indicating an attribute of the data area. The attribute area consists of a first flag indicating whether or not data is stored in the data area, a second flag indicating whether or not data written in the data area is valid, and a third flag indicating whether or not data written in the data area is stored as a block. When an instruction supplied from a host system is a valid-data rearrangement instruction, the control CPU refers to the second flag, and sets a first flag of a data area whose second flag indicates that data is invalid to indicate that data is unwritten, thus rear-ranging valid data of the data memory so that no invalid data area is present between valid data areas.
    Type: Grant
    Filed: October 23, 1986
    Date of Patent: January 24, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuo Iijima
  • Patent number: 4419145
    Abstract: In a process for producing at least one Nb.sub.3 Sn superconductor which comprises drawing a composite composed of a core of niobium or a niobium alloy and a matrix of a copper-tin alloy and subjecting the drawn composite to reactive heat-treatment, thereby forming a layer of Nb.sub.3 Sn between the core and the matrix; the improvement wherein the copper-tin alloy contains 1 to 15 atomic percent of tin, and 0.1 to 8 atomic percent in total of at least one element selected from 0.1 to 8 atomic percent of titanium, 0.1 to 5 atomic percent of zirconium and 0.1 to 5 atomic percent of hafnium.
    Type: Grant
    Filed: July 28, 1982
    Date of Patent: December 6, 1983
    Assignee: National Research Institute for Metals
    Inventors: Kyoji Tachikawa, Hisashi Sekine, Kikuo Itoh, Yasuo Iijima
  • Patent number: 4293739
    Abstract: A switching network has a group of incoming lines respectively connected to the terminal equipments of a plurality of subscriber stations. A group of outgoing lines are respectively connected to a plurality of trunk circuits. A plurality of crosspoints are formed between the incoming lines and the outgoing lines. Crosstalk is eliminated between mutually adjacent incoming lines or between mutually adjacent outgoing lines, by serially connecting a series circuit between the lines where crosstalk might otherwise occur. The serial circuit includes a phase inverter circuit and an impedance element having an impedance value which is sufficiently close to that of the impedance which is likely to cause crosstalk between these lines.
    Type: Grant
    Filed: January 29, 1980
    Date of Patent: October 6, 1981
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Yasuo Iijima
  • Patent number: 4239835
    Abstract: A magnetic recording medium wherein a ferromagnetic substance consisting of Fe, Co, Ni or alloy thereof is vacuum evaporated and deposited on a substrate made of a plastic film or a sheet of non-magnetic metal. The thin ferromagnetic film has the columnar crystal structure, and the columnar crystals are coated with a layer of oxide of the ferromagnetic substance.
    Type: Grant
    Filed: July 13, 1977
    Date of Patent: December 16, 1980
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuo Iijima, Koichi Shinohara, Takashi Fujita, Masaru Odagiri, Toshiaki Kunieda
  • Patent number: 4068286
    Abstract: An oil-impregnated capacitor comprising a thin insulator sheet solely consisting of a plastic film and impregnated with an insulating oil, the aptitude of which is defined by both the oil absorption and the expansion coefficient of the film.
    Type: Grant
    Filed: August 25, 1976
    Date of Patent: January 10, 1978
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuo Iijima, Tokihiko Shimizu
  • Patent number: 4053941
    Abstract: There is disclosed an oil impregnated electric device in which an element of the device is impregnated with a mixture of an arylalkane compound such as 1,1-phenylxylyl ethane and an organic phosphorus compound such as phosphate or phosphite. Such electric device has a high power density (i.e., capable of withstanding high electric field) and a high reliability.
    Type: Grant
    Filed: June 6, 1975
    Date of Patent: October 11, 1977
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tokihiko Shimizu, Yasuo Iijima, Makoto Kusano