Electrically erasable programmable read-only memory with NAND cell structure

Abstract

An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

Claims

2. The device according to claim 1, wherein said substrate has a first conductivity type, said well region has a second conductivity type.Iadd.,.Iaddend.and said semiconductive layers have the first conductivity type.

3. The device according to claim 1, wherein said substrate and said well region have a first conductivity type and said semiconductive layers have a second conductivity type; and wherein said device further comprises an additional well region of the second conductivity type formed in said substrate so as to surround said well region.

4. The device according to claim 3, wherein said well regions are connected to a common well potential.

6. The device according to claim 1, wherein each of said NAND cell blocks comprises:

an erase gate layer provided insulatingly over said substrate so as to extend substantially parallel to said series array of memory cell transistors and sandwiched insulatingly by said charge accumulation layer and said control gate of each of said memory cell transistors, said erase gate layer overlapping said charge accumulation layer.Iadd.,.Iaddend.and said charge accumulation layer and said control gate being capacitively coupled to each other by said erase gate layer.

8. The device according to claim 7, wherein said driving means writes data into memory cells of said NAND cell block in a predetermined sequence in which a cell transistor adjacent to said second selection transistor is subjected to writing first and a cell transistor adjacent to said first selection transistor is subjected to writing last.

9. The device according to claim 8, wherein said driving means applies, when a certain memory cell of said NAND cell block is subjected to writing, to said control gate of said certain memory cell a first voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well layer and to the remaining memory cells of said NAND cell block a second voltage lower than the first voltage.

10. The device according to claim 9, wherein said substrate has a first conductivity type, said well layer has a second conductivity type.Iadd.,.Iaddend.and said semiconductive layers have the first conductivity type.

11. The device according to claim 10, wherein said driving means applies to said well layer one of a "H" level potential and a "L" level potential during the simultaneous erase mode and the other of the "H" level potential and the "L" level potential during the data write mode.

12. The device according to claim 9, wherein said substrate and said well layer have a first conductivity type and said semiconductive layers have a second conductivity type; and wherein said device further comprises an additional well layer of the second conductivity type formed in said substrate so as to surround said well layer.

14. The device according to claim 1, wherein said control means erases data stored in all said memory cells simultaneously during a data erase mode of said memory device.

16. A nonvolatile semiconductor memory device comprising:

(a) a semiconductor substrate having a major surface;

(b) a semiconductor well region formed in said surface of said substrate, said well region being provided separate from a well region in which transistors are formed to constitute a peripheral circuit of said memory device;

(c) parallel bit lines provided above said substrate;

(d) rewritable memory cells connected to said bit lines, said memory cells comprising NAND cell blocks each of which has a series array of memory cell transistors, each of said memory cell transistors having a charge accumulation layer, a control gate and semiconductor layers formed in said well region to function as sources and drains;

(e) at least first selection transistors included in said NAND cell blocks, each of said first selection transistors provided at one end of said series array of memory cell transistors, and said first selection transistors being formed in said well region in which said NAND cell blocks are formed; and

(f) control means for writing data into memory cells of a selected NAND cell block sequentially during a data write mode subsequent to a data erase mode, said control means applying, when a certain memory cell of said selected NAND cell block is subjected to writing, to said control gate of said certain memory cell a voltage to form such a strong electric field as to allow the transfer of charges between said charge accumulation layer of said certain memory cell and said well region..Iaddend..Iadd.17. The device according to claim 16, wherein said substrate has a first conductivity type, said well region has a second conductivity type, and said semiconductor layers have the first conductivity type..Iaddend..Iadd.18. The device according to claim 16, wherein said substrate and said well region have a first conductivity type and said semiconductor layers have a second conductivity type; and wherein said device further comprises an additional well region of the second conductivity type formed in said substrate so as to surround said well region..Iaddend..Iadd.19. The device according to claim 18, wherein said well regions are connected to a common well potential..Iaddend..Iadd.20. The device according to claim 16, wherein said selected NAND cell block further comprises:

second selection transistors included in said NAND cell blocks, each of said second selection transistors provided at the other end of said series array of memory cell transistors, and said second selection transistors being formed in said well region in which said NAND cell blocks are formed..Iaddend..Iadd.21. The device according to claim 16, wherein each of said NAND cell blocks comprises:

an erase gate layer provided insulatingly over said substrate so as to extend substantially parallel to said series array of memory cell transistors and sandwiched insulatingly by said charge accumulation layer and said control gate of each of said memory cell transistors, said erase gate layer overlapping said charge accumulation layer, and said charge accumulation layer and said control gate being capacitively coupled to each other by said erase gate layer..Iaddend..Iadd.22. The device according to claim 20, wherein:

said first selection transistors are selectively rendered conductive for electrically connecting said series array of memory cell transistors to a corresponding bit line associated therewith; and

said second selection transistors are selectively rendered conductive for electrically connecting said series array of memory cell transistors to a source potential and are rendered nonconductive during the data write mode so as to prevent flow of current in said corresponding bit line..Iaddend.