Abstract: A silicon carbide substrate has a substrate region and a support portion. The substrate region has a first single crystal substrate. The support portion is joined to a first backside surface of the first single crystal. The dislocation density of the first single crystal substrate is lower than the dislocation density of the support portion. At least one of the substrate region and the support portion has voids.

Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing a SiC substrate made of single-crystal silicon carbide; disposing a base substrate in a crucible so as to face a main surface of the SiC substrate; and forming a base layer made of silicon carbide in contact with the main surface of the SiC substrate, by heating the base substrate in the crucible to fall within a range of temperature higher than a sublimation temperature of silicon carbide constituting the base substrate. In the step of forming the base layer, a gas containing silicon is introduced into the crucible.

Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing a SiC substrate made of single-crystal silicon carbide; disposing a base substrate in a crucible so as to face a main surface of the SiC substrate; and forming a base layer made of silicon carbide in contact with the main surface of the SiC substrate by heating the base substrate in the crucible to fall within a range of temperature equal to or higher than a sublimation temperature of silicon carbide constituting the base substrate. The crucible has an inner wall at least a portion of which is provided with a coating layer made of silicon carbide.

Abstract: A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; fabricating a stacked substrate by placing said SiC substrate on and in contact with a main surface of said base substrate; and connecting said base substrate and said SiC substrate to each other by heating said stacked substrate in a container to fall within a range of temperature equal to or greater than a sublimation temperature of silicon carbide constituting said base substrate. In the step of connecting said base substrate and said SiC substrate, a silicon carbide body made of silicon carbide and different from said base substrate and said SiC substrate is disposed in said container.

Abstract: A supporting portion is made of silicon carbide. At least one layer has first and second surfaces. The first surface is supported by the supporting portion. The at least one layer has first and second regions. The first region is made of silicon carbide of a single-crystal structure. The second region is made of graphite. The second surface has a surface formed by the first region. The first surface has a surface formed by the first region, and a surface formed by the second region. In this way, a semiconductor substrate can be provided which has a region made of silicon carbide having a single-crystal structure and a supporting portion made of silicon carbide and allows for reduced electric resistance of an interface therebetween.

Abstract: A base portion and first and second silicon carbide substrates are disposed in a processing chamber such that a first side surface of a first silicon carbide substrate and a side surface of a second silicon carbide substrate face each other. The processing chamber has an inner surface at least a portion of which is covered with an absorbing portion including Ta atoms and C atoms. In order to connect the first and second side surfaces to each other, a temperature in the processing chamber is increased to reach or exceed a temperature at which silicon carbide can sublime. In the step of increasing the temperature, at least a portion of the absorbing portion is carbonized.

Abstract: A silicon carbide substrate has a first layer facing a semiconductor layer and a second layer stacked on the first layer. Dislocation density of the second layer is higher than dislocation density of the first layer. Thus, quantum efficiency and power efficiency of a light-emitting device can both be high.

Abstract: A base portion is made of silicon carbide and has a main surface. At least one silicon carbide layer is provided on the main surface of the base portion in a manner exposing a region of the main surface along an outer edge of the main surface. At least one protection layer is provided on this region of the main surface of the base portion along the outer edge of the main surface. Thus, a silicon carbide substrate can be polished with high in-plane uniformity.

Abstract: A first silicon carbide substrate having a first back-side surface and a second silicon carbide substrate having a second back-side surface are prepared. The first and second silicon carbide substrates are placed so as to expose each of the first and second back-side surfaces in one direction. A connecting portion is formed to connect the first and second back-side surfaces to each other. The step of forming the connecting portion includes a step of forming a growth layer made of silicon carbide on each of the first and second back-side surfaces, using a sublimation method of supplying a sublimate thereto in the one direction.

Abstract: A lateral junction field-effect transistor capable of preventing the occurrence of leakage current and realizing a sufficient withstand voltage can be provided. In a lateral JFET according to the present invention, a buffer layer is located on a main surface of a SiC substrate and includes a p-type impurity. A channel layer is located on the buffer layer and includes an n-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. A source region and a drain region are of n-type and formed to be spaced from each other in a surface layer of the channel layer, and a p-type gate region is located in the surface layer of the channel layer and between the source region and the drain region. A barrier region is located in an interface region between the channel layer and the buffer layer and in a region located under the gate region and includes a p-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer.

Abstract: A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

Abstract: On a p? epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p? epitaxial layer a voltage that causes a reverse biased state of the p? epitaxial layer and the n-type epitaxial layer in an OFF operation.

Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.

Abstract: A process of heat-treating II-VI compound semiconductors reduces the electrical resistivity without the decrease in crystallinity resulting from the increase in dislocation density. The process comprises the following steps:(a) placing at least one II-VI compound semiconductor in contact with aluminum in a heat-treating chamber having the inside surface formed by at least one material selected from the group consisting of pyrolytic born nitride, hexagonal-system boron nitride, sapphire, alumina, aluminum nitride, and polycrystalline diamond; and (b) heat-treating the II-VI compound semiconductor or semiconductors in a gaseous atmosphere containing the group II element constituting part of the II-VI compound semiconductor or semiconductors. A II-VI compound semiconductor is heat-treated by the foregoing process. An apparatus for heat-treating II-VI compound semiconductors comprises components for performing the foregoing process.

Abstract: A process of heat-treating II-VI compound semiconductors reduces the electrical resistivity without the decrease in crystallinity resulting from the increase in dislocation density. The process comprises the following steps:(a) placing at least one II-VI compound semiconductor in contact with aluminum in a heat-treating chamber having the inside surface formed by at least one material selected from the group consisting of pyrolytic born nitride, hexagonal-system boron nitride, sapphire, alumina, aluminum nitride, and polycrystalline diamond; and (b) heat-treating the II-VI compound semiconductor or semiconductors in a gaseous atmosphere containing the group II element constituting part of the II-VI compound semiconductor or semiconductors. A II-VI compound semiconductor is heat-treated by the foregoing process. An apparatus for heat-treating II-VI compound semiconductors comprises components for performing the foregoing process.

Abstract: This invention relates to a method for the heat treatment of a ZnSe crystal substrate to dope it with Al as a donor impurity, a ZnSe crystal substrate prepared by this heat treatment and a light-emitting device using the ZnSe crystal substrate, in particular, the method for the heat treatment of a ZnSe crystal substrate comprising previously forming an Al film on the substrate, first subjecting the substrate to a heat treatment in a Se atmosphere and then subjecting to a heat treatment in a Zn atmosphere.

Abstract: This invention relates to a method for the heat treatment of a ZnSe crystal substrate to dope it with Al as a donor impurity, a ZnSe crystal substrate prepared by this heat treatment and a light-emitting device using the ZnSe crystal substrate, in particular, the method for the heat treatment of a ZnSe crystal substrate comprising previously forming an Al film on the substrate, first subjecting the substrate to a heat treatment in a Se atmosphere and then subjecting to a heat treatment in a Zn atmosphere.

Abstract: A clamp-type isolating pipe joint is disclosed, which can connect pipes by providing insulation between them, is easy to assemble and disassemble, has high reliability and allows easy replacement of parts and is inexpensive to manufacture and install. The joint comprises hubs weldable to connectable pipes, a seal ring interposed between butted surfaces of the hubs and a clamp disposed around the circumferences of the hubs for clamping itself with bolts in the radial direction of the hubs to be fixed as insulated from each other. The clamp and hubs are insulated by interposing between them a metal plate with an insulating resin coat formed thereon. Insulation layers are also provided between the seal ring and the hubs.

Abstract: A large oxide crystal of high quality is manufactured by increasing the speed of crystal growth without affecting crystal growth. A melt of BaO--CuO as a raw material put in a crucible is heated and melt in the presence of a solid phase precipitate of Y.sub.2 BaCuO.sub.5 and kept at a prescribed temperature. Thereafter, a seed crystal is pulled up while being rotated, with the seed crystal being in contact with the surface of the melt, whereby an oxide crystal having the structure of YBa.sub.2 Cu.sub.3 O.sub.7-x this method, an atmosphere for growing the oxide crystal has an oxygen partial pressure higher than that in an ambient atmosphere.

Abstract: A crystal pulling apparatus is designed to generate a thermal gradient across the melt surface to prevent nucleation of stray crystals and production of floating debris to produce a high quality crystal, and has special provisions for observing the growth behavior and crystal dimension measurements. The apparatus includes a cylindrical chamber, a crucible disposed centrally within the chamber, a cylindrical heater surrounding the crucible, an insulation member disposed on the top section of the crucible, a first transparent plate and a second transparent plate for closing the center hole in the insulation member, a pull rod passing through the center hole of the transparent plates, a crystal illumination mechanism, a crystal size determination mechanism and an ambient atmosphere flowing mechanism.