Patents by Inventor Yasuo Satoh
Yasuo Satoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10601410Abstract: Several embodiments of electrical circuit devices and systems with a duty cycle correction apparatus that includes a duty cycle adjustment circuit that is configured to adjust a duty cycle of the input clock signal based on an averaged code value. The duty cycle correction apparatus includes a duty cycle detector circuit that receives first and second clock signals from a clock distribution network. The duty cycle detector is configured to output a duty cycle status signal that indicates whether the first clock signal is above or below a 50% duty cycle based on a comparison of the first clock signal to the second clock signal. The duty cycle correction apparatus also includes a counter logic circuit configured to determine the average code value, and the counter logic circuit automatically cancels an offset of the duty cycle detector when determining the averaged code value.Type: GrantFiled: November 2, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventor: Yasuo Satoh
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Patent number: 10594328Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.Type: GrantFiled: May 8, 2019Date of Patent: March 17, 2020Assignee: Micron Technology, Inc.Inventor: Yasuo Satoh
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Patent number: 10560108Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.Type: GrantFiled: June 13, 2019Date of Patent: February 11, 2020Assignee: Micron Technology, Inc.Inventor: Yasuo Satoh
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Patent number: 10529390Abstract: A memory system includes an external calibration device that has a predetermined impedance and a first memory device with a first pad for selective connection to the external calibration device. The first memory device also includes an internal calibration device having an impedance that is programmable and a second pad connected to the internal calibration device. The system further includes a second memory device having a third pad for selective connection to the second pad of the first memory device. A processing device is operatively coupled to the first memory device and the second memory device. The processing device programs the impedance of the internal calibration device of the first memory device based on the external calibration device, and programs an impedance of a termination component in the second memory device based on the impedance of the internal calibration device of the first memory device.Type: GrantFiled: November 30, 2018Date of Patent: January 7, 2020Assignee: Micron Technology, Inc.Inventors: Yasuo Satoh, Yuan He
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Publication number: 20200005855Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.Type: ApplicationFiled: August 30, 2019Publication date: January 2, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Yasuo Satoh, Tyler J. Gomm
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Patent number: 10516391Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.Type: GrantFiled: December 12, 2017Date of Patent: December 24, 2019Assignee: Micron Technology, Inc.Inventors: Yasuo Satoh, Kazutaka Miyano
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Publication number: 20190363724Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.Type: ApplicationFiled: August 8, 2019Publication date: November 28, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Yasuo Satoh
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Patent number: 10461759Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.Type: GrantFiled: September 19, 2018Date of Patent: October 29, 2019Assignee: Micron Technology, Inc.Inventor: Yasuo Satoh
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Patent number: 10438648Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.Type: GrantFiled: January 11, 2018Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventors: Yasuo Satoh, Tyler J. Gomm
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Publication number: 20190296752Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.Type: ApplicationFiled: June 13, 2019Publication date: September 26, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Yasuo Satoh
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Publication number: 20190288674Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.Type: ApplicationFiled: March 16, 2018Publication date: September 19, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: Yasuo Satoh
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Publication number: 20190268009Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.Type: ApplicationFiled: May 8, 2019Publication date: August 29, 2019Inventor: Yasuo Satoh
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Publication number: 20190214072Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Yasuo Satoh, Tyler J. Gomm
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Publication number: 20190207592Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.Type: ApplicationFiled: March 6, 2019Publication date: July 4, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Tyler J. Gomm, Yasuo Satoh
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Publication number: 20190199364Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.Type: ApplicationFiled: October 3, 2018Publication date: June 27, 2019Applicant: Micron Technology, Inc.Inventor: Yasuo Satoh
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Patent number: 10333532Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.Type: GrantFiled: September 7, 2017Date of Patent: June 25, 2019Assignee: Micron Technology, Inc.Inventor: Yasuo Satoh
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Patent number: 10333534Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.Type: GrantFiled: October 3, 2018Date of Patent: June 25, 2019Assignee: Micron Technology, Inc.Inventor: Yasuo Satoh
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Publication number: 20190181847Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Applicant: Micron Technology, Inc.Inventors: Yasuo Satoh, Kazutaka Miyano
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Patent number: 10270431Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.Type: GrantFiled: September 27, 2017Date of Patent: April 23, 2019Assignee: Micron Technology, Inc.Inventors: Tyler J. Gomm, Yasuo Satoh
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Publication number: 20190115928Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second arid third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.Type: ApplicationFiled: September 19, 2018Publication date: April 18, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: YASUO SATOH