Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.

Abstract: Apparatuses and methods are disclosed for detecting a loop count in a delay-locked loop that uses a divide clock in a measure initialization process. An example apparatus includes a divider configured to receive a signal and produce a first divided signal and a second divided signal that is complementary to the first divided signal, a first circuit configured to count the first divided signal during a first enabled period and produce a first count value, a second circuit configured to count the second divided signal during a second enabled period and produce a second count value, and an adder configured to produce a third count value responsive to the first and second count values.

Abstract: Apparatuses and methods for providing frequency divided clocks are described. An example apparatus includes a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock and further includes a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock. The apparatus further includes a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks.

Abstract: Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

Abstract: Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device. In an embodiment, each die may include a respective assignment device to operate on an input and generate, as an output, the respective one of the sequence of the unique device ID values. Each die may also include a respective evaluation device to detect a total number of dice in the stack. Additional apparatuses and methods are described.

Abstract: Methods and apparatuses are disclosed for preserving duty cycle at voltage domain boundaries. One example apparatus includes a complement generation circuit configured to generate a complementary signal responsive to an input signal. The complement generation circuit is configured to operate in a first voltage domain. The apparatus also includes a compensation circuit configured to generate a compensated signal by compensating the input signal for a delay corresponding to the complement generation circuit. The compensation circuit is configured to operate in a second voltage domain. The apparatus also includes a phase mixing circuit configured to combine the complementary signal and the compensated signal to generate an output signal.

Abstract: Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.

Abstract: Methods and apparatuses are disclosed for preserving duty cycle at voltage domain boundaries. One example apparatus includes a complement generation circuit configured to generate a complementary signal responsive to an input signal. The complement generation circuit is configured to operate in a first voltage domain. The apparatus also includes a compensation circuit configured to generate a compensated signal by compensating the input signal for a delay corresponding to the complement generation circuit. The compensation circuit is configured to operate in a second voltage domain. The apparatus also includes a phase mixing circuit configured to combine the complementary signal and the compensated signal to generate an output signal.

Abstract: The present invention provides an ethylene polymer composition having a particularly high formability and having an excellent mechanical strength, a shaped article formed of such an ethylene polymer, and a film and multilayer film having a particularly excellent blocking resistance. An ethylene polymer composition (?) according to the present invention includes a specific ethylene polymer (?) that is a copolymer of ethylene and an ?-olefin having 4 to 10 carbon atoms and an ethylene polymer (?) that is a copolymer of ethylene and an ?-olefin having 4 to 10 carbon atoms but different from the ethylene polymer (?), and weight fraction [W?] of the ethylene polymer (?) is in the range of not less than 0.1 and not more than 0.9, and weight fraction [W?] of the ethylene polymer (?) is in the range of not less than 0.1 and not more than 0.9 (the sum of the W? and the W? is 1.0).

Abstract: According to the invention, a single or plural kinds of bridged metallocene compounds having differing cyclopentadienyl-derived groups afford macromonomers that are a source of long-chain branches and simultaneously catalyze the repolymerization of the macromonomers into olefin polymers having a large number of long-chain branches, small neck-in in the T-die extrusion, small take-up surge and superior mechanical strength. The olefin polymerization catalysts and the polymerization processes can efficiently produce the olefin polymers.

Abstract: Metallocene compounds of the invention are useful as olefin polymerization catalysts or catalyst components. Olefin polymerization processes of the invention involve an olefin polymerization catalyst containing the metallocene compound. In detail, the olefin polymerization catalysts can catalyze with high polymerization activity the production of olefin polymers having high melt tension, excellent mechanical strength and good particle properties, and the olefin polymerization processes involve the catalysts. Ethylene polymers according to the invention are obtained by the polymerization processes and have higher processability and easy-opening properties and particularly excellent mechanical strength compared to conventional ethylene polymers. Thermoplastic resin compositions of the invention contain the ethylene polymers.

Abstract: Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device. In an embodiment, each die may include a respective assignment device to operate on an input and generate, as an output, the respective one of the sequence of the unique device ID values. Each die may also include a respective evaluation device to detect a total number of dice in the stack. Additional apparatuses and methods are described.

Abstract: Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the duty cycle adjustor. First and second phase detectors have first inputs coupled to the duty cycle adjustor through an inverter and second inputs coupled to the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: The present invention provides a film including, in at least a part thereof, a layer comprising an ethylene-based resin, which is a copolymer of ethylene and an ?-olefin of 4 to 10 carbon atoms, and satisfies the following requirements (1) to (5) at the same time or an ethylene-based resin composition containing the resin; (I) the melt flow rate at 190° C. under a load of 2.16 kg is in the range of 0.1 to 50 g/10 min, (II) the density is in the range of 875 to 970 kg/m3, (III) the ratio of a melt tension at 190° C. to a shear viscosity at 200° C. and an angular velocity of 1.0 rad/sec is in the range of 1.00×10?4 to 9.00×10?4, (IV) the sum of the number of methyl branches and the number of ethyl branches, each number being based on 1000 carbon atoms and measured by 13C-NMR, is not more than 1.8, and (V) the zero shear viscosity [?0(P)] at 200° C. and the weight-average molecular weight (Mw) as measured by a GPC-viscosity detector method (GPC-VISCO) satisfy the following relational formula (Eq-1): 0.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the duty cycle adjustor. First and second phase detectors have first inputs coupled to the duty cycle adjustor through an inverter and second inputs coupled to the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: Ethylene-based resin, which exhibits a satisfactorily high melt tension and can provide a molded object excellent in mechanical strength, the ethylene-based resin characterized in simultaneously satisfying the requirements [1] to [5] described below: [1] melt flow rate (MFR) under a loading of 2.16 kg at 190° C. is in the range of 0.1 to 100 g/10 minutes; [2] density (d) is in the range of 875 to 970 kg/m3; [3] ratio [MT/?*(g/P)] of melt tension [MT(g)] at 190° C. to shearing viscosity [?*(P)] at 200° C. at an angular velocity of 1.0 rad/sec. is in the range of 1.50×10?4 to 9.00×10?4; [4] sum [(A+B)(/1000C)] of the number of methyl branches [A(/1000C)] and the number of ethyl branches [B(/1000C)] per 1000 carbon atoms measured by 13C-NMR is 1.8 or less; and [5] zero shear viscosity [?0(P)] at 200° C. and weight-average molecular weight (Mw) measured by GPC-viscosity detector method (GPC-VISCO) satisfy the following relational expression (Eq-1): 0.01×10?13×Mw3.4??0?4.5×10?13×Mw3.4??(Eq-1).