Patents by Inventor Yasushi Akasaka
Yasushi Akasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070190767Abstract: In a method for manufacturing a semiconductor device, an insulating film is formed on an entire surface of a substrate having a device isolation region and a first and a second conductive region. Then, a semiconductor device structure having a gate electrode forming region is formed on each of the conductive regions, the insulating film being disposed between the gate electrode forming region and each of the conductive regions. A gate electrode groove is formed in the gate electrode forming region of the semiconductor device structure, the insulating film being removed in the gate electrode groove. Thereafter, a gate insulating film and a film of metal gate electrode material are deposited on a bottom surface and a side surface of the gate electrode groove and an alloy is formed by alloying the film of metal gate electrode material deposited in a gate electrode groove of the first conductive region.Type: ApplicationFiled: February 9, 2007Publication date: August 16, 2007Applicant: TOKYO ELECTRON LIMITEDInventors: Genji Nakamura, Yasushi Akasaka
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Publication number: 20070172997Abstract: There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.Type: ApplicationFiled: March 9, 2007Publication date: July 26, 2007Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
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Patent number: 7232751Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.Type: GrantFiled: February 2, 2005Date of Patent: June 19, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
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Patent number: 7208797Abstract: There is provided a semiconductor device including a substrate, a device isolation insulating film formed on the substrate, a gate electrode formed on the substrate, a gate wiring layer formed in the device isolation insulating film and connected to the gate electrode, source and drain electrodes arranged on the substrate to face each other via the gate electrode, and an insulating film covering bottom and side surfaces of each of the gate electrode and the gate wiring layer, wherein the gate, source and drain electrodes and gate wiring layer have upper surface levels equal to or lower than that of the device isolation insulating film.Type: GrantFiled: December 21, 2001Date of Patent: April 24, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
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Publication number: 20070066077Abstract: A method for manufacturing a semiconductor device includes doping a surface of a silicon-containing dielectric film with nitrogen to change an etching rate of the silicon-containing dielectric film relative to a predetermined solution such that the etching rate is lower at a surface portion doped with nitrogen than at a portion therebelow. The method subsequently includes patterning the silicon-containing dielectric film by a first etching process to form an etching mask, subsequently to the first etching process, removing etching residues of the silicon-containing dielectric film by a second etching process including wet etching using the predetermined solution, and subsequently to the second etching process, patterning an etching target film by a third etching process using the etching mask.Type: ApplicationFiled: September 20, 2006Publication date: March 22, 2007Inventors: Yasushi Akasaka, Genji Nakamura
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Publication number: 20060166427Abstract: A method of manufacturing a semiconductor device comprises: forming a device isolation, a first conductivity type region, and a second conductivity type region on a semiconductor substrate; depositing a gate insulating film on an entire surface of the semiconductor substrate; forming a first metal film on the gate insulating film; forming a region of a second metal film so as to cover a region that forms a gate electrode of the first conductivity type region; removing the first metal film exposed outside the region of the second metal film by wet etching to expose the gate insulating film; forming a third metal film on the entire surface of the semiconductor substrate; depositing a protecting film on the third metal film; and patterning the first metal film, the second metal film, the third metal film, and the protecting film to form the gate electrode.Type: ApplicationFiled: December 28, 2005Publication date: July 27, 2006Inventor: Yasushi Akasaka
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Patent number: 7078776Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.Type: GrantFiled: June 16, 2004Date of Patent: July 18, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazumi Nishinohara, Yasushi Akasaka, Kyoichi Suguro
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Patent number: 7071529Abstract: A semiconductor device includes semiconductor elements and at least one dummy pattern. Each or at least some of the semiconductor elements has a Damascene gate structure or a replacing gate structure and is located in element-forming regions. In addition, at least a dummy pattern is located in a region different from the element-forming regions. The dummy pattern may have a semiconductor element structure of the same or different kind from the Damascene gate structure or replacing gate structure. The dummy pattern may be a pattern of an insulating film, an interface transistor, or an analog circuit capacitor electrode instead of the dummy gate.Type: GrantFiled: June 9, 2004Date of Patent: July 4, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Kazuhiro Miyagawa, Mitsuo Yasuhira, Yasushi Akasaka, Isamu Nishimura
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Publication number: 20060081939Abstract: A semiconductor device having a metal insulator semiconductor field effect transistor (MISFET) with increased electron mobility and enhanced hole mobility is disclosed. In this semiconductor device, a p-type well layer and an n-type well layer are formed in a surface portion of a silicon substrate. A nitrogen-nondoped n-channel interface layer and a nitrogen-free n-channel high dielectric constant gate insulation film plus an n-channel gate electrode are formed in an n-channel MISFET as partitioned by an element isolation region. And, n-type source/drain diffusion layers are provided. In a p-channel MISFET, a nitrogen-doped p-channel interface layer, a nitrogen-added p-channel high dielectric gate insulation film and a p-channel gate electrode are formed along with p-channel source/drain diffusion layers as provided therein. A method of fabricating this semiconductor device is also disclosed.Type: ApplicationFiled: September 9, 2005Publication date: April 20, 2006Inventors: Yasushi Akasaka, Kazuhiro Miyagawa, Takaoki Sasaki
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Patent number: 6989316Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.Type: GrantFiled: April 4, 2003Date of Patent: January 24, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
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Publication number: 20060011950Abstract: Disclosed is a semiconductor device comprises a semiconductor substrate having on its surface a trench, a polycrystalline semiconductor film formed inside the trench, a diffusion layer deposited on a surface region of the semiconductor substrate, and a metal semi-conductor nitride layer interposed between the diffusion layer and the polycrystalline semiconductor film, the metal semiconductor nitride layer including a metal, nitrogen and a semiconductor constituting the semiconductor substrate, and electrically connecting the polycrystalline semiconductor film with the diffusion layer.Type: ApplicationFiled: August 30, 2005Publication date: January 19, 2006Inventor: Yasushi Akasaka
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Patent number: 6956259Abstract: Disclosed is a semiconductor device comprises a semiconductor substrate having on its surface a trench, a polycrystalline semiconductor film formed inside the trench, a diffusion layer deposited on a surface region of the semiconductor substrate, and a metal semiconductor nitride layer interposed between the diffusion layer and the polycrystalline semiconductor film, the metal semiconductor nitride layer including a metal, nitrogen and a semiconductor constituting the semiconductor substrate, and electrically connecting the polycrystalline semiconductor film with the diffusion layer.Type: GrantFiled: June 11, 2003Date of Patent: October 18, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Yasushi Akasaka
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Patent number: 6939787Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.Type: GrantFiled: October 13, 2004Date of Patent: September 6, 2005Assignees: Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Fumio Ohtake, Yasushi Akasaka, Atsushi Murakoshi, Kyoichi Suguro
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Publication number: 20050167767Abstract: A semiconductor apparatus comprises a first semiconductor device and a second semiconductor device. The first semiconductor device includes: a semiconductor layer having a p-type channel area; an n-type source area, and an n-type drain area; a first gate insulating film provided on the p-type channel area; and a first gate electrode provided on the first gate insulating film containing a first metallic element and nitrogen. The second semiconductor device includes: a semiconductor layer having an n-type channel area, a p-type source area, and a p-type drain area; a second gate insulating film provided on the n-type channel area; and a second gate electrode provided on the second gate insulating film containing a second metallic element and nitrogen. A nitrogen content of the second gate electrode is higher than a nitrogen content of the first gate electrode.Type: ApplicationFiled: January 28, 2005Publication date: August 4, 2005Applicant: Semiconductor Leading Edge Technologies , Inc.Inventor: Yasushi Akasaka
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Publication number: 20050130418Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.Type: ApplicationFiled: February 2, 2005Publication date: June 16, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
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Patent number: 6893980Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.Type: GrantFiled: November 8, 2000Date of Patent: May 17, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
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Publication number: 20050082605Abstract: A gate insulating film is formed in a first region and a second region of a substrate, a first metallic film is formed on the gate insulating film in one of the first region or the second region, and a second metallic film is formed on each of the first and second regions. Furthermore, a protective film is formed on the second metallic film, and the protective film and the metallic film are patterned to the pattern of the gate electrode. Next, a first sidewall is formed on the side of a gate electrode. Then, impurities producing first and second conductivity types are implanted into the surface of the substrate in respective regions, using the first sidewalls and the gate electrodes as masks to form a first impurity-diffused region, and impurities producing second and first conductivity types are implanted to form an impurity diffusion preventing layer.Type: ApplicationFiled: October 13, 2004Publication date: April 21, 2005Applicant: Semiconductor Leading Edge Technologies, Inc.Inventor: Yasushi Akasaka
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Publication number: 20050062115Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.Type: ApplicationFiled: October 13, 2004Publication date: March 24, 2005Applicants: FUJITSU LIMITED, KABUSHIKI KAISHA TOSHIBAInventors: Fumio Ohtake, Yasushi Akasaka, Atsushi Murakoshi, Kyoichi Suguro
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Publication number: 20050001267Abstract: A semiconductor device includes semiconductor elements and at least one dummy pattern. Each or at least some of the semiconductor elements has a Damascene gate structure or a replacing gate structure and is located in element-forming regions. In addition, at least a dummy pattern is located in a region different from the element-forming regions. The dummy pattern may have a semiconductor element structure of the same or different kind from the Damascene gate structure or replacing gate structure. The dummy pattern may be a pattern of an insulating film, an interface transistor, or an analog circuit capacitor electrode instead of the dummy gate.Type: ApplicationFiled: June 9, 2004Publication date: January 6, 2005Applicant: Semiconductor Leading Edge Technologies, Inc.Inventors: Kazuhiro Miyagawa, Mitsuo Yasuhira, Yasushi Akasaka, Isamu Nishimura
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Publication number: 20040238883Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities, whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.Type: ApplicationFiled: June 16, 2004Publication date: December 2, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Kazumi Nishinohara, Yasushi Akasaka, Kyoichi Suguro