Patents by Inventor Yasushi Akasaka
Yasushi Akasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6770944Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.Type: GrantFiled: November 26, 2002Date of Patent: August 3, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Kazumi Nishinohara, Yasushi Akasaka, Kyoichi Suguro
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Publication number: 20040070045Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.Type: ApplicationFiled: July 22, 2003Publication date: April 15, 2004Applicant: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
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Publication number: 20040026727Abstract: Disclosed is a semiconductor device comprises a semiconductor substrate having on its surface a trench, a polycrystalline semiconductor film formed inside the trench, a diffusion layer deposited on a surface region of the semiconductor substrate, and a metal semiconductor nitride layer interposed between the diffusion layer and the polycrystalline semiconductor film, the metal semiconductor nitride layer including a metal, nitrogen and a semiconductor constituting the semiconductor substrate, and electrically connecting the polycrystalline semiconductor film with the diffusion layer.Type: ApplicationFiled: June 11, 2003Publication date: February 12, 2004Inventor: Yasushi Akasaka
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Publication number: 20030211713Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.Type: ApplicationFiled: April 4, 2003Publication date: November 13, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
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Patent number: 6617226Abstract: In using an epitaxial growth method to selectively grow on a silicon substrate an epitaxial layer on which an element is to be formed, the epitaxial layer is formed so as to extend upward above a thermal oxide film that is an element isolating insulating film, in order to prevent formation of facets. Subsequently, unwanted portions of the epitaxial layer are removed by means of CMP to complete an STI element isolating structure.Type: GrantFiled: June 30, 2000Date of Patent: September 9, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Kyoioni Suguro, Kiyotaka Miyano, Ichiro Mizushima, Yoshitaka Tsunashima, Takayuki Hiraoka, Yasushi Akasaka, Tsunetoshi Arikado
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Publication number: 20030122203Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.Type: ApplicationFiled: November 26, 2002Publication date: July 3, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Kazumi Nishinohara, Yasushi Akasaka, Kyoichi Suguro
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Patent number: 6541829Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.Type: GrantFiled: December 1, 2000Date of Patent: April 1, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Kazumi Nishinohara, Yasushi Akasaka, Kyoichi Suguro
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Publication number: 20020056874Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.Type: ApplicationFiled: December 28, 2000Publication date: May 16, 2002Inventors: Fumio Ohtake, Yasushi Akasaka, Atsushi Murakoshi, Kyoichi Suguro
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Publication number: 20020045296Abstract: A method of manufacturing a semiconductor device according to this invention is characterized by including the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.Type: ApplicationFiled: December 21, 2001Publication date: April 18, 2002Applicant: Kabushika Kaisha ToshibaInventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
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Patent number: 6346438Abstract: A method of manufacturing a semiconductor device according to this invention is characterized by including the steps of a) forming, on one major surface of a substrate, a gate structure constituted by either one of a dummy gate electrode and a gate electrode having an insulating film at least on bottom surface, and a device isolation insulating film so as to form a first groove divided by the dummy gate electrode or the gate electrode, to position the dummy gate electrode or the gate electrode in the first groove, and to form the gate structure to have an upper surface level not higher than an upper level of the device isolation insulating film, and b) forming source and drain electrodes in the first groove.Type: GrantFiled: June 29, 1998Date of Patent: February 12, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Yagishita, Kouji Matsuo, Yasushi Akasaka, Kyoichi Suguro, Yoshitaka Tsunashima
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Publication number: 20010009292Abstract: A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region.Type: ApplicationFiled: December 1, 2000Publication date: July 26, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumi Nishinohara, Yasushi Akasaka, Kyoichi Suguro
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Patent number: 6162741Abstract: According to the manufacturing method of the semiconductor device of the present invention, an oxide film is formed on a metal film formed on a main surface of a semiconductor substrate by exposing the metal film to the oxidizing gas. The oxide film is then reduced in a reducing atmosphere, and a protection film is formed on the surface of the metal film reduced in the reducing step. In this manner, the damage to the surface of the metal film can be prevented.Type: GrantFiled: December 2, 1997Date of Patent: December 19, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Yasushi Akasaka, Kazuaki Nakajima, Kiyotaka Miyano, Kyoichi Suguro
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Patent number: 6133150Abstract: A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.Type: GrantFiled: March 15, 1999Date of Patent: October 17, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Kazuaki Nakajima, Yasushi Akasaka, Kiyotaka Miyano, Kyoichi Suguro
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Patent number: 6100193Abstract: A MOSFET in which the gate electrode is formed of a polycrystalline silicon film, a silicon nitride film having a nitrogen surface density of lens than 8.times.10.sup.14 cm.sup.-2, and a tungsten film--these films formed one upon another in the order mentioned. The gate electrode thus formed, serves to shorten the delay time of the MOSFET.Type: GrantFiled: September 24, 1997Date of Patent: August 8, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shintaro Suehiro, Yasushi Akasaka, Kyoichi Suguro, Kazuaki Nakajima, Tadashi Iijima
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Semiconductor device with conductive oxidation preventing film and method for manufacturing the same
Patent number: 5907188Abstract: A semiconductor device includes a semiconductor substrate, and a laminated film insulatively formed over the semiconductor substrate, wherein the laminated film includes a semiconductor film, a metal film of refractory metal formed on the semiconductor film, a conductive oxidation preventing film disposed between the metal film and the semiconductor film, for preventing oxidation of the semiconductor film in an interface between the metal film and the semiconductor film, and an oxide film formed on a side surface of the semiconductor film and formed to extend into upper and lower portions of the semiconductor film in a bird's beak form.Type: GrantFiled: August 22, 1996Date of Patent: May 25, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kazuaki Nakajima, Yasushi Akasaka, Kiyotaka Miyano, Kyoichi Suguro -
Patent number: 5903027Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.Type: GrantFiled: August 13, 1997Date of Patent: May 11, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
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Patent number: 5903053Abstract: A semiconductor device comprising a conductive layer and an amorphous alloy layer formed on the bottom surface of said conductive layer and acting as a barrier layer. The conductive layer is either an electrode layer or a wiring layer. The amorphous alloy layer is made of a matrix phase and microcrystal grains. The matrix phase consists mainly of a Ti--Si--N amorphous alloy. The microcrystal grains are dispersed in the matrix phase, not continuously arranged in the direction of thickness of the amorphous alloy layer.Type: GrantFiled: July 9, 1996Date of Patent: May 11, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Iijima, Hisako Ono, Kyoichi Suguro, Yasushi Akasaka, Shinichi Nakamura
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Patent number: 5898203Abstract: A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: July 30, 1997Date of Patent: April 27, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5766965Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: December 5, 1994Date of Patent: June 16, 1998Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5719410Abstract: A MOSFET in which the gate electrode is formed of a polycrystalline silicon film, a silicon nitride film having a nitrogen surface density of lens than 8.times.10.sup.14 cm.sup.-2, and a tungsten film--these films formed one upon another in the order mentioned. The gate electrode thus formed, serves to shorten the delay time of the MOSFET.Type: GrantFiled: December 16, 1996Date of Patent: February 17, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Shintaro Suehiro, Yasushi Akasaka, Kyoichi Suguro, Kazuaki Nakajima, Tadashi Iijima