Patents by Inventor Yasushi Ishii
Yasushi Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9640546Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: January 30, 2015Date of Patent: May 2, 2017Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20160372537Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.Type: ApplicationFiled: September 2, 2016Publication date: December 22, 2016Inventors: Yoshiyuki KAWASHIMA, Koichi TOBA, Yasushi ISHII, Toshikazu MATSUI, Takashi HASHIMOTO
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Patent number: 9461105Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.Type: GrantFiled: March 3, 2015Date of Patent: October 4, 2016Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kawashima, Koichi Toba, Yasushi Ishii, Toshikazu Matsui, Takashi Hashimoto
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Patent number: 9443991Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.Type: GrantFiled: March 6, 2016Date of Patent: September 13, 2016Assignee: Renesas Electronics CorporationInventors: Kota Funayama, Hiraku Chakihara, Yasushi Ishii
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Publication number: 20160190350Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.Type: ApplicationFiled: March 6, 2016Publication date: June 30, 2016Inventors: Kota FUNAYAMA, Hiraku CHAKIHARA, Yasushi ISHII
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Patent number: 9379127Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.Type: GrantFiled: June 19, 2015Date of Patent: June 28, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koichi Toba, Yasushi Ishii, Hiraku Chakihara, Kota Funayama, Yoshiyuki Kawashima, Takashi Hashimoto
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Publication number: 20160118352Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.Type: ApplicationFiled: December 30, 2015Publication date: April 28, 2016Inventor: Yasushi Ishii
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Patent number: 9324883Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.Type: GrantFiled: September 7, 2014Date of Patent: April 26, 2016Assignee: Renesas Electronics CorporationInventors: Kota Funayama, Hiraku Chakihara, Yasushi Ishii
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Publication number: 20160079160Abstract: The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side.Type: ApplicationFiled: November 24, 2015Publication date: March 17, 2016Inventors: Yasushi Ishii, Hiraku Chakihara
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Patent number: 9230920Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.Type: GrantFiled: February 19, 2015Date of Patent: January 5, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasushi Ishii
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Patent number: 9214350Abstract: The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side.Type: GrantFiled: May 21, 2014Date of Patent: December 15, 2015Assignee: Renesas Electronics CorporationInventors: Yasushi Ishii, Hiraku Chakihara
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Publication number: 20150325583Abstract: A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.Type: ApplicationFiled: July 18, 2015Publication date: November 12, 2015Inventors: Kota Funayama, Hiraku Chakihara, Yasushi Ishii
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Patent number: 9177937Abstract: The present invention aims to provide a lightened reaction absorber or to provide a semiconductor assembling system with further shorter processing time and high productivity or high quality using the lightened reaction absorber. The present invention is based upon a reaction absorber provided with a counter mechanism equipped with a load unit moved in a predetermined direction by a first ball screw, a second ball screw that generates reactive force in a reverse direction to the predetermined direction and a driving unit having a driving motor that drives the first ball screw and the second ball screw, and has a characteristic of including a reaction absorbing unit with one end side equipped with a nut connected to the second ball screw and the other end side fixed to a unit base movable relatively to the counter mechanism.Type: GrantFiled: September 13, 2010Date of Patent: November 3, 2015Assignee: FASFORD TECHNOLOGY CO., LTD.Inventors: Masayuki Mochizuki, Yasushi Ishii
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Patent number: 9159843Abstract: To improve the electric performance and reliability of a semiconductor device. A memory gate electrode of a split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 6a and a silicon film 6b over the metal film 6a. In an upper end part of the metal film 6a, a metal oxide portion 17 is formed by oxidation of a part of the metal film 6a. A control gate electrode of the split gate type nonvolatile memory is a metal gate electrode formed from a stacked film of a metal film 4a and the silicon film 4b over the metal film 4a.Type: GrantFiled: May 21, 2012Date of Patent: October 13, 2015Assignee: Renesas Electronics CorporationInventors: Kentaro Saito, Kazumasa Yanagisawa, Yasushi Ishii, Koichi Toba
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Publication number: 20150287736Abstract: A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film,. and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.Type: ApplicationFiled: June 19, 2015Publication date: October 8, 2015Inventors: Koichi Toba, Yasushi Ishii, Hiraku Chakihara, Kota Funayama, Yoshiyuki Kawashima, Takashi Hashimoto
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Patent number: 9099334Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.Type: GrantFiled: November 26, 2013Date of Patent: August 4, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasushi Ishii, Hiraku Chakihara, Kentaro Saito
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Patent number: 9093319Abstract: A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.Type: GrantFiled: May 10, 2012Date of Patent: July 28, 2015Assignee: Renesas Electronics CorporationInventors: Kota Funayama, Hiraku Chakihara, Yasushi Ishii
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Publication number: 20150171160Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.Type: ApplicationFiled: March 3, 2015Publication date: June 18, 2015Inventors: Yoshiyuki KAWASHIMA, Koichi TOBA, Yasushi ISHII, Toshikazu MATSUI, Takashi HASHIMOTO
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Publication number: 20150162284Abstract: To improve reliability of a semiconductor device obtained through a dicing step. In a ring region, a first outer ring is provided outside a seal ring, and a second outer ring is provided outside the first outer ring. This can prevent a crack from reaching even the seal ring that exists in the ring region, for example, when a scribe region located outside the ring region is cut off by a dicing blade.Type: ApplicationFiled: February 19, 2015Publication date: June 11, 2015Inventor: Yasushi ISHII
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Publication number: 20150137215Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: January 30, 2015Publication date: May 21, 2015Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI