Patents by Inventor Yasushi Ishii
Yasushi Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7687850Abstract: This invention is to improve data retention properties of a nonvolatile memory cell having an ONO film. A first cavity is disposed, in a position between the nitride film serving as a charge storage film and a memory gate and below an end portion of the memory gate, adjacent to the upper oxide film. A second cavity is disposed, in a position between the nitride film and a substrate and below an end portion of the memory gate, adjacent to the bottom oxide film. These cavities are closed with sidewall spacers formed over the substrate along the sidewalls of the memory gate.Type: GrantFiled: April 13, 2007Date of Patent: March 30, 2010Assignee: Renesas Technology Corp.Inventors: Yasushi Ishii, Takashi Hashimoto, Koichi Toba, Yoshiyuki Kawashima
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Publication number: 20100059810Abstract: The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.Type: ApplicationFiled: August 2, 2009Publication date: March 11, 2010Inventors: Takuro HOMMA, Yasushi Ishii, Kota Funayama
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Publication number: 20100038700Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: October 16, 2009Publication date: February 18, 2010Inventors: Tsutomu OKAZAKI, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Patent number: 7663176Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: GrantFiled: May 2, 2008Date of Patent: February 16, 2010Assignee: Renesas Technology Corp.Inventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Patent number: 7636253Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: January 16, 2009Date of Patent: December 22, 2009Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20090256193Abstract: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.Type: ApplicationFiled: June 23, 2009Publication date: October 15, 2009Inventors: YASUSHI ISHII, Takashi Hashimoto, Yoshiyuki Kawashima, Koichi Toba, Satoru Machida, Kozo Katayama, Kentaro Saito, Toshikazu Matsui
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Patent number: 7595893Abstract: A shape measurement method for measuring a shape of an object to be measured, which has a substantially rotating symmetric shape, includes: placing an aperture having an opening larger than an outer shape of the object to be measured and the object to be measured on an optical axis; taking an image generated by light projected to the object to be measured, by using an image pickup unit; and calculating one cross-sectional shape of the object to be measured based on a light intensity distribution of the image taken by the image pickup unit.Type: GrantFiled: September 17, 2007Date of Patent: September 29, 2009Assignee: Mitutoyo CorporationInventors: Sotomitsu Hara, Yutaka Tsuchida, Yoshikazu Arai, Yasushi Ishii, Makoto Abe, Yasushi Ueshima
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Patent number: 7557005Abstract: In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.Type: GrantFiled: March 27, 2007Date of Patent: July 7, 2009Assignee: Renesas Technology Corp.Inventors: Yasushi Ishii, Takashi Hashimoto, Yoshiyuki Kawashima, Koichi Toba, Satoru Machida, Kozo Katayama, Kentaro Saito, Toshikazu Matsui
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Publication number: 20090122609Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: ApplicationFiled: January 16, 2009Publication date: May 14, 2009Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATA, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
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Publication number: 20090102059Abstract: Increase in the chip size of a semiconductor device is suppressed. The semiconductor device includes: circuit vias provided in an interlayer insulating film between upper and lower wiring layers and coupling these wiring layers together; a planar ring-shaped protecting via that is provided in the interlayer insulating film under an electrode pad and one side of which is coupled with the electrode pad; a protecting wiring layer comprised of a wiring layer coupled only with the other side of the protecting via; and a semiconductor element provided over the principal surface of a semiconductor substrate under the protecting wiring layer. The lower part of the electrode pad whose surface is exposed is encircled with the protecting via and the protecting wiring layer. The width of the protecting via is equal to or larger than the width of each circuit via.Type: ApplicationFiled: September 28, 2008Publication date: April 23, 2009Inventor: Yasushi ISHII
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Publication number: 20090095995Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.Type: ApplicationFiled: September 28, 2008Publication date: April 16, 2009Inventors: Yoshiyuki KAWASHIMA, Koichi TOBA, Yasushi ISHII, Toshikazu MATSUI, Takashi HASHIMOTO
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Patent number: 7502257Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: May 1, 2007Date of Patent: March 10, 2009Assignee: Renesas Technology Corp.Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
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Publication number: 20090001449Abstract: The present invention provides a technology capable of reducing an area occupied by a nonvolatile memory while improving the reliability of the nonvolatile memory. In a semiconductor device, the structure of a code flash memory cell is differentiated from that of a data flash memory cell. More specifically, in the code flash memory cell, a memory gate electrode is formed only over the side surface on one side of a control gate electrode to improve a reading speed. In the data flash memory cell, on the other hand, a memory gate electrode is formed over the side surfaces on both sides of a control gate electrode. By using a multivalued memory cell instead of a binary memory cell, the resulting data flash memory cell can have improved reliability while preventing deterioration of retention properties and reduce its area.Type: ApplicationFiled: June 3, 2008Publication date: January 1, 2009Inventors: Koichi Toba, Yasushi Ishii, Yoshiyuki Kawashima, Takashi Hashimoto, Kosuke Okuyama
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Publication number: 20080206975Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: May 2, 2008Publication date: August 28, 2008Inventors: Takeshi SAKAI, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Publication number: 20080203466Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: ApplicationFiled: May 2, 2008Publication date: August 28, 2008Inventors: Takeshi SAKAI, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Publication number: 20080151629Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.Type: ApplicationFiled: January 25, 2008Publication date: June 26, 2008Inventors: Fumitoshi ITO, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
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Patent number: 7371631Abstract: For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film.Type: GrantFiled: June 29, 2005Date of Patent: May 13, 2008Assignee: Renesas Technology Corp.Inventors: Takeshi Sakai, Yasushi Ishii, Tsutomu Okazaki, Masaru Nakamichi, Toshikazu Matsui, Kyoya Nitta, Satoru Machida, Munekatsu Nakagawa, Yuichi Tsukada
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Patent number: 7349250Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.Type: GrantFiled: July 15, 2005Date of Patent: March 25, 2008Assignee: Renesas Technology Corp.Inventors: Fumitoshi Ito, Yoshiyuki Kawashima, Takeshi Sakai, Yasushi Ishii, Yasuhiro Kanamaru, Takashi Hashimoto, Makoto Mizuno, Kousuke Okuyama, Yukiko Manabe
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Publication number: 20080068608Abstract: A shape measurement method for measuring a shape of an object to be measured, which has a substantially rotating symmetric shape, includes: placing an aperture having an opening larger than an outer shape of the object to be measured and the object to be measured on an optical axis; taking an image generated by light projected to the object to be measured, by using an image pickup unit; and calculating one cross-sectional shape of the object to be measured based on a light intensity distribution of the image taken by the image pickup unit.Type: ApplicationFiled: September 17, 2007Publication date: March 20, 2008Applicant: MITUTOYO CORPORATIONInventors: Sotomitsu Hara, Yutaka Tsuchida, Yoshikazu Arai, Yasushi Ishii, Makoto Abe, Yasushi Ueshima
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Publication number: 20080029825Abstract: Even if it is the semiconductor device provided with the wiring on an isolation insulating film, the sidewall formed on the side surface of this wiring, and the shared contact which connects the wiring and the impurity diffusion on an active region, the semiconductor device which can suppress the generation of the leakage current from shared contact to a semiconductor substrate, and its manufacturing method are offered.Type: ApplicationFiled: August 2, 2007Publication date: February 7, 2008Inventors: Kentaro Saito, Yasushi Ishii, Munekatsu Nakagawa, Satoru Machida, Masaru Nakamichi