Abstract: A flash memory (100) includes a core cell array (104), address decoders (116), one or more output buffers (110) and sensing circuitry including sense amplifiers which sense data at an address selected by the address decoders. A data switching multiplexer (108) is coupled to the output buffers to select a sense amplifier for a current word of data in response to a control signal (RWDEN) . A control circuit (106) is coupled to the data switching multiplexer to provide the control signal at a time to ensure the current word of data is provided to the output buffers.

Abstract: Data lines are wired next to each other. A sense amplifier receives the data and outputs an amplified signal. Dummy data lines are laid out along both sides of a data bus consisting of the data lines. The dummy data lines have the same voltage variation as the data lines during a read operation of the data stored in the memory cells. This reduces the potential differences between the data lines and the dummy data lines during a read operation. As a result, the outer data lines and the inner data lines become nearly equal to each other in coupling characteristics, and the lengths of time it takes for the data read to each of the data lines to rise become almost equal to each other. Since the data lines have smaller fluctuations in rising time, the read time (access time) is accelerated.

Abstract: A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option 18, a bank selector encoder 2 coupled to receive a memory partition indicator signal from the memory boundary option 18, and a bank selector decoder 3 coupled to receive a bank selector code from the bank selector encoder 2. The decoder 3, upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

Abstract: An alterable Common Flash Interface (“CFI”) is disclosed which includes a storage array which stores the CFI data. The storage array provides sub-circuits for encoding the CFI data. The sub-circuits comprise elements which can be altered by changing a single metal layer of the fabrication process.

Abstract: A high voltage comparator circuit quickly identifies the voltage level of the predetermined voltages required for program operations. Through the series of transistors, the precise timing of when the predetermined voltages are at their operating voltage level is identified.

Abstract: An alterable Common Flash Interface ("CFI") is disclosed which includes a storage array which stores the CFI data. The storage array provides sub-circuits for encoding the CFI data. The sub-circuits comprise elements which can be altered by changing a single metal layer of the fabrication process.

Abstract: A simultaneous operation flash memory capable of write protecting predetermined sectors in the simultaneous operation flash memory. The preferred simultaneous operation flash memory includes a plurality of sectors divided into an upper bank and a sliding lower bank. Each bank is associated with a predetermined amount of sectors in the simultaneous operation flash memory. The simultaneous operation flash memory also includes at least one upper address decoder circuit that has a upper sector select line. During operation, each upper address decoder circuit generates a predetermined output signal on the upper sector select line when selected. In addition, the simultaneous operation flash memory includes at least one lower address decoder circuit including a lower address sector select line, wherein each upper address decoder circuit generates a predetermined output signal on the lower sector select line when selected during operation.

Abstract: A reference voltage generator circuit is provided for use with an extremely low power supply voltage. The reference voltage generator circuit produces a lower reference output voltage which is compensated for temperature variations and is independent of changes in the supply voltage. The reference output voltage relies upon the threshold voltage V.sub.T of a MOSFET transistor as a reference source.

Abstract: A method of forming flexibly partitioned metal line segments 10 and 12 for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer 2 comprising a plurality of basic metal layer segments 2a, 2b, 2c, . . . 2j separated by a plurality of gaps 6a, 6b, 6c, . . . 6i, each of the gaps having a predefined gap interval length, and providing a metal option layer 8 comprising a plurality of metal option layer segments on the basic metal layer 2, the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.

Abstract: A decoding circuit 54 for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder 44, a lower bank decoder 58, an upper bank decoder 56, and a plurality of flexibly partitioned conductive lines coupled between the upper and lower bank decoders 56 and 58. The flexibly partitioned conductive lines 60, 62, 64, . . . 74 provide a plurality of bank address pre-decoding bits for the X-decoder 44 to row decode the memory cells along the respective word lines in the memory array 20. The memory array 20 includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are coupled to two Y-decoders 32 and 34 which provide column decoding for the memory cells in the upper and lower memory banks.

Abstract: A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array 20 including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines 28 and 30 each coupled to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder 22 coupled to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders 24 and 26 are coupled to the X-decoder 22. Two Y-decoders 32 and 34 are coupled to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.

Abstract: A flash memory performs channel erasing or source erasing by applying a negative voltage to a control gate. The device includes a voltage restriction device which restricts the negative voltage to be applied to the control gate so that the negative voltage will be a constant value relative to the voltage of the channel or source. Alternatively, two voltage restricting devices restrict the negative voltage applied to the control gate and the voltage to be applied to the source so that the voltages will be a constant value relative to a common reference voltage.

Abstract: A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2" word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective.

Abstract: A substrate voltage control circuit is used to apply bias voltage to a substrate or a well of a semiconductor memory such as a flash memory. The substrate voltage control circuits do not use any depletion type transistors. Therefore, the area occupied by the transistors for the circuit is small.

Abstract: A negative-voltage circuit for realizing a flash memory is installed independently and is applied selectively to word lines in response to signals sent from row decoders. Row decoders for specifying word lines need not be installed in the negative voltage circuit. The negative circuit can therefore be reduced in scale.

Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

Abstract: The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3, . . . , whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.