Abstract: There is disclosed an active matrix liquid crystal display that receives input signals having small amplitudes and needs no externally attached level-shifting circuit. The active matrix liquid crystal display has a level-shifting circuit for amplifying various input signals, such as control signals, a clock signal, and a start pulse signal, and supplying the amplified signals to peripheral driver circuits. These peripheral driver circuits drive an active matrix circuit. The level-shifting circuit is made of a differential amplifier consisting of polysilicon TFTs. This amplifier is an analog amplifier. This level-shifting circuit is fabricated on the same substrate as the active matrix circuit and the peripheral driver circuits. If the amplitudes of the input signals are small, level-shifting operations can be performed well. Since any externally attached level-shifting circuit is dispensed with, the cost can be curtailed.

Abstract: A position measuring laser apparatus includes first and second laser transmitter-receivers and a position measure. The laser transmitter-receiver includes a laser beam emitter for emitting a laser beam, and a laser beam receiver for receiving a laser beam resulting from the emitted laser beam reflected from a reference reflecting mirror. An optical axis of the laser transmitter-receiver is oriented at a required angle toward a moving body. The position of the moving body-with respect to the reference reflecting mirror is measured based on a beam receiving signal of the laser beam obtained by the laser transmitter-receiver. The position measure compares a drive signal for driving the laser beam emitter with a beam receiving signal generated by the laser beam receiver to measure the position of the moving body based on the beam receiving signal when the drive signal and the beam receiving signal coincide with each other.

Abstract: The surface area occupied by a digital type signal line driver circuit in an image display device is large, and this is an impediment to reducing the size of the display device. A memory circuit within a signal line driver circuit is made common among n signal lines (where n is a natural number greater than or equal to 2). One horizontal scan period is divided into n divisions, and all signal lines can be driven by performing processing with respect to signal lines differing by memory circuit and D/A converter circuit, respectively, during the period of each division. It thus becomes possible to make 1/n as many memory circuits and D/A conversion circuits within the signal line driver circuit as in a conventional example.

Abstract: In an anodic oxidization method of the invention for anodizing areas including and surrounding a plurality of gate electrodes connected to a current supply line by respective gate connecting lines, the current supply line supplies currents to the gate electrodes in a manner that the densities of anodizing currents flowing through corresponding parts of any two parallel-running neighboring gate electrodes arranged in a semiconductor island area become substantially equal to each other. No leakage current flows from one gate electrode to another because the anodizing currents are supplied in such a way that no potential difference occurs between any two neighboring gate electrodes during anodic oxidization as a result of differences in current path length. This makes it possible to prevent crystal defects and partial anodization imperfections which could potentially be caused by leakage currents.

Abstract: A delay detecting section detects the phase difference between a first detection signal as a reference and a second detection signal produced by delaying the first detection signal with part of a data signal line driving circuit itself or part of a circuit formed by the same process as the data signal line driving circuit. A phase adjusting section presumes an internal delay of the data signal line driving circuit, and adjusts the phase difference between a clock signal and start signal, and a video signal so that the data signal line driving circuit samples the video signal at an appropriate timing. These structures prevent a lowering of the image quality due to a difference in the timings of the video signal and sampling signal, and provide an image display device capable of displaying a good-quality image with a simple circuit structure.

Abstract: A semiconductor device includes a first conductive layer; an interlayer insulative layer having an opening; and a second conductive layer. The first conductive layer, the interlayer insulative layer and the second conductive layer are sequentially laminated. The opening is partially covered by the second conductive layer, and an area of the first conductive layer is substantially entirely covered by the second conductive layer in the opening.

Abstract: A driving circuit of a liquid crystal display device including a first insulating substrate on which a plurality of signal lines and a plurality of scan lines are disposed, and pixel transistors made of thin film transistors are disposed in matrix at intersection points of those lines; a second insulating substrate opposite to the first insulating substrate; and a liquid crystal held between the first and second insulating substrates, in which the driving circuit is disposed on the first insulating substrate; each of clock lines or base portions of the clock lines for supplying clock signals to the driving circuit is made of a two-layer structure of the same wiring material as a gate electrode of the thin film transistor and the same wiring material as a source electrode or drain electrode of the thin film transistor; and a wiring line crossing the clock lines or the base portions of the clock lines is made of a wiring line in the same layer as a black matrix covering the pixel transistors.

Abstract: An active-matrix-type image display device having a gray-scale power supply for generating gray-scale voltages of different levels, and a source driver that applies gray-scale voltages according to a digital picture signal to source lines and includes one scanning circuit for each source line. The outputs of the scanning circuits are sequentially made active once in a horizontal period. A latch circuit fetches the digital picture signal in synchronization with making the output of the scanning circuit active. The digital picture signal is decoded by a decoder circuit, and one of analog switches becomes a conducting state according to the decoded signal. As a result, one of the gray-scale voltages is output to the source line.

Abstract: There is provided a shift register circuit of a wide operation margin capable of reducing a capacitive load of a clock signal line, reducing a load of external circuits and achieving consumption power reduction and cost reduction with a simple construction, and an imaging display device including it. A plurality of serially connected register blocks BLK2 has a D-type flip-flop DFF1 that operates in synchronization with a clock signal, transfer gates TG11 and TG12 for controlling clock signals CK and /CK supplied to the D-type flip-flop DFF1 and an exclusive-OR circuit XOR1 that outputs a control signal to the transfer gates TG11 and TG12 so that the transfer gates are brought into an ON-state only in a specified period during which the output of the D-type flip-flop DFF1 changes i.e. when the input signal level and the output signal level of the D-type flip-flop DFF1 differ from each other.

Abstract: A voltage level shifter comprises complementary transistors T1, T2 connected between a supply line vdd and an inverting input !IN. The gate of the transistor T1 is connected to a direct signal input IN whereas the gate of the transistor T2 receives a shifted version of the direct input signal from a source-follower comprising the transistors T3 and T4. The level shifter may also be embodied as a differential cross-coupled sense amplifier with the sources of the drain load transistors being crossed coupled to the differential inputs.

Abstract: In a field-effect transistor, one of the distance between a gate electrode and a source electrode and the distance between the gate electrode and a drain electrode which one distance is on a side where a signal of a high frequency is applied is made longer than the other distance on a side where a signal of a low frequency is applied.

Abstract: A sampling circuit is arranged so that source voltages VDD and VEE, which are to be applied to two inverters at the latter stages in a signal path on the p-channel transistor side, are shifted to the positive side with respect to source voltages VCC and VSS that are applied to the other inverters. With such a power supply construction, video signals on the low-potential side in a video signal line are picked up by the n-channel transistor and video signals on the high-potential side are picked up by the p-channel transistor, and the resulting signals are supplied to a data signal line. This arrangement makes it possible to reduce the gate input voltage upon conduction of the sampling switch. Moreover, by shifting the levels of the source voltages as described above, it becomes possible to ensure writing and holding operations even in the case of having signals with a small amplitude.

Abstract: A flow channel and pressure equalizing sections introduce a fluid having substantially no angular momentum into a thrust balance chamber of a thrust balance device. The introduction of this fluid reduces the angular momentum of the fluid in the thrust balance chamber, facilitating the discharge of fluid out of the thrust balance chamber through a variable orifice. The thrust balance chamber exerts a variable pressure onto a rear surface of an impeller of a centrifugal pump. This pressure prevents significant displacement of the impeller during pump operation. The result is a centrifugal pump having good thrust balance properties regardless of flow rate and impeller speed.

Abstract: A matrix-type image display device of the present invention is arranged such that image data are selectively applied to pixels arranged in a matrix form through scanning signal lines and data signal lines, and the image data are stored therein, wherein a high potential of a sampling pulse 0V/5V to be output from a logic circuit is shifted to 10 V, and a low potential thereof is shifted to -8 V respectively by first and second level shifters. As a result, a difference between an input signal level from an external circuit such as a control circuit, an image signal processing circuit, etc., and an actual driving signal level of each pixel can be absorbed. Therefore, an additional structure such as an interface circuit, etc., is not needed between the external circuit and the scanning signal line driving circuit, thereby enabling a low cost and a low power consumption.

Abstract: An air bag (11) for a side air bag device capable of reducing the size and weight of the device (M1) while retaining a tension line (L--L) when expanded is mounted on the peripheral edge of a door opening (W) at the inside of a compartment, and is formed into a generally rectangular bag shape for covering the door opening when expanded, while being equipped with a gas inlet (19) for introducing an expanding gas. The air bag is provided with joints (22) jointing an inner side wall (12) and an outer side wall (13) partially so as to form a tension line L--L when expanded. The individual joints (22) are juxtaposed in plurality along the tension line so as to cross the tension line, and are arranged generally at vertically middle portions so as to form one expansion chamber (18) having upper and lower spaces (18a and 18b) for the expanding gas to flow therethrough.

Abstract: A voltage output circuit has decoders, a selecting circuit, a logical circuit and an output circuit in order to select one of plural gradation power source lines for a prescribed period based upon k bits and m bits of an n-bit digital signal. The k bits of the digital signal are converting into 2.sup.k decoded signals by one decoder, and another m bits are converted into 2.sup.m decoded signals by the other decoder. The selecting circuit generates a signal for selecting one of periods which were obtained by dividing one horizontal scanning period into 2.sup.k based upon k-numbered timing signals by using the 2.sup.k decoded signals. The logical circuit generates 2.sup.n signals composed of combinations of the signals from the selecting circuit and the 2.sup.m decoded signals. Moreover, one of the 2.sup.m gradation power source lines is selected by an output switch by using the signal from the logical circuit.

Abstract: An active-matrix image display device which includes n shift registers, analog switches for sampling video input signals and a data-signal-line driving circuit to which n series of clock signals and n.times.m series of video input signals are input, and controls the analog switches according to the result of a logic operation of output pulses from successive l stages in the shift registers. A scanning circuit without using shift registers. Here, n is an integer not smaller than one, m and l are integers not smaller than two. With the image display device, sampling of video signals is surely executed without increasing the number of shift registers. It is thus possible to reduce the size and weight of the image display device and to decrease the defect rate thereof. Moreover, the scanning circuit achieves a higher yield compared with a conventional scanning circuit using a shift register.

Abstract: An active matrix liquid crystal display includes a rectangular array of picture elements driven by data and scan drivers. Each picture element includes a liquid crystal display element connected to the output of a unity gain buffer amplifier. The input of the amplifier is connected to a hold capacitor and to series connected gate transistors. The gates of the transistors are connected to a scan electrode and the transistors are connected in series between a data electrode and the input of the amplifier. The output of the amplifier is connected to the connection between the transistors.

Abstract: An image display device includes an operational amplifier, a signal amplifier provided with a condenser for setting a gain of the operational amplifier, a signal amplifier circuit having such signal amplifier or a buffer amplifier, the signal amplifier circuit being provided with an offset adjusting function, and a data signal line drive circuit having a signal amplifier or a signal line drive circuit. The described arrangement enables the gain of the signal amplifier to be set by a capacitance of the condenser, thereby providing a signal amplifier circuit which permits the gain to be set much more precisely as compared to the conventional signal amplifier circuits even when adopting a signal amplifier formed on a semiconductor thin film such as a polycrystalline silicone thin film. The arrangement also provides a signal amplifier circuit which permits a voltage in the same level as a voltage of the input signal to be outputted.

Abstract: A scanning circuit for a display device having an array of pixels. One embodiment of the scanning circuit includes L scan control signal lines, first logic circuits to operate on signals from M of the L scan control signal lines, flip-flop circuits communicating with the first logic circuits, N timing control signal lines, and second logic circuits coupled to operate on signal from the N timing control signal lines and the flip-flop circuits.