Abstract: A clip for attaching a curtain-shield airbag to a body panel of a vehicle comprises a bushing and a pin. The bushing has a flange with a leg extending therefrom. A bore extends through the flange and into the leg for receiving the pin. Outer surfaces of the leg have engagement pieces with shoulders for coupling the bushing to edge regions of a body panel hole into which the leg is inserted. The pin and the bushing are capable of being coupled in a provisionally fixed condition or a permanently fixed condition. When the pin is partially inserted into the bore, the engagement pieces are permitted to flex inwardly of the bore, but when the pin is fully inserted, such inward flexing is prevented. The flange has a wall that provides a partition between the main airbag unit and the entrance hole of the bore in the flange.

Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

Abstract: The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are different. Level shift circuit 10 that outputs the output signal of the high voltage source as a response to the input signal of the low voltage source has the following attribute: When feeding of the low voltage source is delayed with respect to feeding of the high voltage source, on the basis of the high voltage source, power-on-reset circuit 20 generates power-on-reset signal PWR. During the period before the input signal of the low voltage source is fed as a response to power-on-reset PWR, latch circuit 30 initializes the level shift circuit, and holds its output OUT at the low level.

Abstract: In a shift register provided with flip-flops that operate in synchronism with a clock signal, and a switching means, which is opened and closed in response to an output of the preceding stage of each of the flip-flops, is installed. The clock signal is selectively inputted by the switching means, and the selected clock signal is inverted and used as a shift register output from each of the stages. Moreover, two kinds of clock signals, each of which has a duty ratio of not more than 50% and which have no overlapped portions in their low-level periods, are used so as to prevent the outputs of the shift-register from overlapping each other. Thus, it is possible to provide a shift register which is preferably used for a driving circuit of an image display device, can miniaturize the driving circuit, and can desirably change the pulse width of the output signal, and also to provide an image display device using such a shift register.

Abstract: A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts.

Abstract: A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.

Abstract: A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

Abstract: A method for stabilizing 1,4-dihydroxy-2-naphthoic acid, which comprises reducing an oxygen dissolved in a solution containing 1,4-dihydroxy-2-naphthoic acid, and food or drink containing 1,4-dihydroxy-2-naphthoic acid.

Abstract: A method for producing an extract and/or a squeezed liquid, which comprises: feeding a food to be extracted and/or squeezed into a crushing apparatus; adding a solvent into the crushing apparatus immediately after and/or while milling the food; extracting and/or squeezing a useful food component of the food into the solvent; and carrying out liquid-solid separation by removing the resulting extracted residue and/or squeezed residue with a continuous solid-liquid separation apparatus.

Abstract: A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring.

Abstract: Before a potential of counter electrode is changed, a potential holding circuit fixedly holds potentials of data signal lines S during a non-selective period of scanning signal lines G. This prevents the potentials of the data signal lines S from being an undesirably large potential, which is caused by coupling capacitors between the counter electrode and each data signal line S, whereby it is possible to supply to the pixel capacitor an electric charge corresponding to a gradation to be displayed, by using the relatively low potentials of the data signal lines S. This lowers a power supply voltage of a data signal driving circuit SD, thus reducing the electric power consumption. In short, with this arrangement, a liquid crystal display device can perform an opposed AC drive for line-inversion drive, frame-inversion drive and the like, by low power supply voltage of the data signal line driving circuit SD, thereby reducing the electric power consumption.

Abstract: A driving circuit of a liquid crystal display device including a first insulating substrate on which a plurality of signal lines and a plurality of scan lines are disposed, and pixel transistors made of thin film transistors are disposed in matrix at intersection points of those lines; a second insulating substrate opposite to the first insulating substrate; and a liquid crystal held between the first and second insulating substrates, in which the driving circuit is disposed on the first insulating substrate; each of clock lines or base portions of the clock lines for supplying clock signals to the driving circuit is made of a two-layer structure of the same wiring material as a gate electrode of the thin film transistor and the same wiring material as a source electrode or drain electrode of the thin film transistor; and a wiring line crossing the clock lines or the base portions of the clock lines is made of a wiring line in the same layer as a black matrix covering the pixel transistors.

Abstract: A display panel drive circuit and a display panel are provided which are simple in structure but free from initial failure leading to impossibility to perform scanning. The display panel drive circuit of the present invention is structured such that thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits. Specifically, countermeasures are taken by transistor formation in multi-gate structure, gate width broadening, resistance insertion between an input terminal and a transistor or the like. In the present invention, the circuit to which signals are externally inputted or thin film transistors of the same circuit is structured to withstand high voltage, thereby preventing the transistors from being deteriorated by high voltage and occurrence of initial failure while being simple in structure.

Abstract: A signal line driving circuit includes a shift register having a plurality of shift circuits, each of which shifts a start pulse successively to the next stage, synchronizing with the timing of a clock signal. In this signal line driving circuit, shift pulses are outputted from an AND gate based on output pulses of two adjacent shift circuits. Meanwhile, a width specifying pulse for specifying a pulse width of the shift pulse is inputted via a transistor whose ON/OFF operation is controlled by the shift pulse. A logical operation circuit operates an AND of the shift pulse and the width specifying pulse and outputs the result of operation to a signal line. When the shift pulse is non-active, the transistor becomes OFF, which causes the signal line transmitting the width specifying pulse to be disconnected from the signal line driving circuit, thereby reducing a capacitive load of wiring.

Abstract: The scanning signal line driving circuit sequentially carries out active driving with respect to each set of a certain number of scanning signal lines which are adjacent to each other in a vertical direction, and when carrying out an actual writing with respect to a first set of a certain number of pixel lines adjacent to each other in the vertical direction, carries out pre-charging with respect to a second set of the certain number of pixel lines to which the actual writing is carried out next with a potential of a same polarity as that of the first set of the certain number of pixel lines. In this manner, it is possible to provide a matrix image display device with no irregularities in display quality and is capable of matching the apparent vertical resolution of the device to that of the image source, when using an image signal of vertical resolution lower than the maximum physical vertical resolution of the device.

Abstract: A process for preparing butter milk and/or butter serum, which comprises decreasing the dissolved oxygen concentration of at least one selected from the group consisting of milk, a milk product, butter milk and butter serum, followed by heating, and optionally fractionizing the heated product.

Abstract: An AC driven active matrix display device in which image display with enough brightness can be easily achieved while reducing an amplitude range of a pixel electrode potential. The display device 1, 100 or 110 according to the invention comprises two memory circuits (a first memory circuit 40 and a second memory circuit 41) which are connected in series between each pixel electrode 22 and a corresponding signal line 30. Data is written to the first memory circuit in a first period, then the data is transferred from the first memory circuit to the corresponding second memory circuit in a second period. The potential of a counter electrode 23 is switched in the second period between a first potential (VcomH) and a second potential (VcomL).

Abstract: The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are different. :evel shift circuit 10 that outputs the output signal of the high voltage source as a response to the input signal of the low voltage source has the following attribute: When feeding of the low voltage source is delayed with respect to feeding of the high voltage source, on the basis of the high voltage source, power-on-reset circuit 20 generates power-on-reset signal PWR. During the period before the input signal of the low voltage source is fed as a response to power-on-reset PWR, latch circuit 30 initializes the level shift circuit, and holds its output OUT at the low level.

Abstract: An image display device includes two data signal line drive circuits and two scan signal line drive circuits configured differently from each other. Different data signal line drive circuits and scan signal line drive circuit are compatible with different display formats. A display can be produced in the most suitable display format, and power consumption also can be reduced, by switch operating drive circuits according to the kind of input video and environmental conditions. Further, an image can be written over another image by writing video signals to signal lines with a time lag using a plurality of drive circuits; therefore, a superimposed display can be produced without externally processing the video signals. Thus, both a satisfactory image display and low power consumption can be achieved in an image display device.