Abstract: A shift register is provided with a shift register section composed of a plurality of stages of flip-flops that operate in synchronization with a clock signal, and level shifters for boosting a start signal lower than a driving voltage and for applying the same to both ends of the shift register section, and the shift register is capable of switching the shift direction in accordance with the switching signal. The foregoing level shifters are current-driving-type level shifters that can operate even in the case where the transistor characteristics are inferior or in the case of fast operations, and that can carry out level shifting even with a start signal having a small amplitude. Furthermore, the foregoing level shifters are provided at both ends of the shift register section, respectively, and one of the same stops operating in accordance with a switching signal, so that consumed power should decrease.

Abstract: The surface area occupied by a digital type signal line driver circuit in an image display device is large, and this is an impediment to reducing the size of the display device. A memory circuit within a signal line driver circuit is made common among n signal lines (where n is a natural number greater than or equal to 2). One horizontal scan period is divided into n divisions, and all signal lines can be driven by performing processing with respect to signal lines differing by memory circuit and D/A converter circuit, respectively, during the period of each division. It thus becomes possible to make 1/n as many memory circuits and D/A conversion circuits within the signal line driver circuit as in a conventional example.

Abstract: A display panel drive circuit and a display panel are provided which are simple in structure but free from initial failure leading to impossibility to perform scanning. The display panel drive circuit of the present invention is structured such that thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits. Specifically, countermeasures are taken by transistor formation in multi-gate structure, gate width broadening, resistance insertion between an input terminal and a transistor or the like. In the present invention, the circuit to which signals are externally inputted or thin film transistors of the same circuit is structured to withstand high voltage, thereby preventing the transistors from being deteriorated by high voltage and occurrence of initial failure while being simple in structure.

Abstract: A position measuring laser apparatus includes first and second laser transmitter-receivers and a position measure. The laser transmitter-receiver includes a laser beam emitter for emitting a laser beam, and a laser beam receiver for receiving a laser beam resulting from the emitted laser beam reflected from a reference reflecting mirror. An optical axis of the laser transmitter-receiver is oriented at a required angle toward a moving body. The position of the moving body with respect to the reference reflecting mirror is measured based on a beam receiving signal of the laser beam obtained by the laser transmitter-receiver. The position measure compares a drive signal for driving the laser beam emitter with a beam receiving signal generated by the laser beam receiver to measure the position of the moving body based on the beam receiving signal when the drive signal and the beam receiving signal coincide with each other.

Abstract: A structure of arranging an vehicle occupant protecting apparatus for an automotive vehicle, which can prevent a pillar garnish from scattering when an air bag installed in a front pillar portion is expanded, is provided. An air bag 16 is housed within a space formed by a front pillar main body 38 and a pillar garnish 40 in a front pillar portion 20. When the air bag 16 expands, the pillar garnish 40 is pressed by an expanding pressure of the air bag 16, so that an opening for expanding the air bag 16 is formed between the front pillar main body 38 and the pillar garnish 40, and the air bag 16 expands into a vehicle cabin through the opening. Since a non-expanding portion is formed at the air bag 16 and a hinge portion 46 is formed at the pillar garnish 40, the expanding pressure applied to the pillar garnish 40 when the air bag 16 expand is low, so that the pillar garnish 40 can be easily opened through the hinge portion 46.

Abstract: A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.

Abstract: A voltage level shifter comprises an input stage in the form of cross-coupled source followers and an output stage in the form of an amplifier AMP, which may have single-ended or differential inputs. The source followers comprise the transistors M1 and M2 and the transistors M3 and M4. Differential inputs IN and !IN are connected to the gates of the transistors M2 and M4. A bias voltage is supplied to the gate of the transistor M1 from a node B to which the drain of the transistor M3 and the source of the transistor M4 are connected. Similarly, a bias voltage is supplied to the gate of the transistor M3 from a node A to which the drain of the transistor M1 and the source of the transistor M2 are connected.

Abstract: A precharge circuit is composed of (a) a reference signal input section, to which at least one precharge reference potential is inputted, (b) a control signal input section, to which at least one control signal is inputted, (c) a plurality of signal delay sections for sequentially delaying an output of the control signal input section, and (d) a reference signal switching section for switching, in accordance with outputs of the signal delay sections, between a state of outputting the precharge reference potential of the reference signal input section to each of the data signal lines and a state of non-outputting the same thereto. With this arrangement, the precharge control signal is sequentially delayed within the precharge circuit by the delay circuits composed of inverter circuits or the like, so that timings at which the precharge reference potential is written in the data signal lines are dispersed.

Abstract: A display panel drive circuit and a display panel are provided which are simple in structure but free from initial failure leading to impossibility to perform scanning. The display panel drive circuit of the present invention is structured such that thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits. Specifically, countermeasures are taken by transistor formation in multi-gate structure, gate width broadening, resistance insertion between an input terminal and a transistor or the like. In the present invention, the circuit to which signals are externally inputted or thin film transistors of the same circuit is structured to withstand high voltage, thereby preventing the transistors from being deteriorated by high voltage and occurrence of initial failure while being simple in structure.

Abstract: A control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area is refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

Abstract: An active matrix display device has a number of pixels arranged in matrix form, signal lines for supplying display signals to the pixels, and a driver circuit for driving the signal lines. The driver circuit includes a frequency divider circuit for frequency-dividing input multi-phase clock signals, a synchronous counter circuit for frequency-dividing part of the input multi-phase clock signals, and a decoder circuit for selecting a desired one of the signal lines based on outputs of the frequency divider circuit and the synchronous counter circuit.

Abstract: If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.

Abstract: A structure of arranging an vehicle occupant protecting apparatus for an automotive vehicle, which can prevent a pillar garnish from scattering when an air bag installed in a front pillar portion is expanded, is provided. An air bag 16 is housed within a space formed by a front pillar main body 38 and a pillar garnish 40 in a front pillar portion 20. When the air bag 16 expands, the pillar garnish 40 is pressed by an expanding pressure of the air bag 16, so that an opening for expanding the air bag 16 is formed between the front pillar main body 38 and the pillar garnish 40, and the air bag 16 expands into a vehicle cabin through the opening. Since a non-expanding portion is formed at the air bag 16 and a hinge portion 46 is formed at the pillar garnish 40, the expanding pressure applied to the pillar garnish 40 when the air bag 16 expand is low, so that the pillar garnish 40 can be easily opened through the hinge portion 46.

Abstract: A matrix type image display device has a structure in which the internal states of all of shift registers (the outputs of flip-flops included in the shift registers) in a scanning signal line drive circuit and data signal line drive circuit are made inactive by the use of an initializing signal generated by a NAND gate based on a combination of signals, which do not affect a displayed image, from a control circuit. With this structure, since the shift registers are initialized when power is supplied, it is possible to prevent an indefinite state when power is supplied. Therefore, by selectively inputting signals (such as clock signals) for controlling the shift registers, it is possible to prevent an excessive increase in the signal line load. Consequently, the operation of the image display device can be stabilized.

Abstract: A digital-to-analog converter includes a first converter stage 1 for converting the m most significant bits of a k bit input signal to upper and lower voltage limits VL and VH by selecting the appropriate low impedance reference voltages. A second converter stage 2 performs a linear conversion of the n least significant bits of the k bit input within the voltage range defined by the voltage limits VL and VH. A precharging circuit including switches SW1 and SW2 disconnects the stage 2 from the load CLOAD, which is charged to the voltage limit VL during the precharge phase. The load is subsequently disconnected from the voltage limit VL and connected to the output of the stage 2 to complete charging of the load CLOAD to the converter output voltage.

Abstract: Before a potential of counter electrode is changed, a potential holding circuit fixedly holds potentials of data signal lines S during a non-selective period of scanning signal lines G. This prevents the potentials of the data signal lines S from being an undesirably large potential, which is caused by coupling capacitors between the counter electrode and each data signal line S, whereby it is possible to supply to the pixel capacitor an electric charge corresponding to a gradation to be displayed, by using the relatively low potentials of the data signal lines S. This lowers a power supply voltage of a data signal driving circuit SD, thus reducing the electric power consumption. In short, with this arrangement, a liquid crystal display device can perform an opposed AC drive for line-inversion drive, frame-inversion drive and the like, by low power supply voltage of the data signal line driving circuit SD, thereby reducing the electric power consumption.

Abstract: A potential of a data signal line S during a scanning period is charged to a substantially intermediate potential of a data signal at a corresponding frame. Thus, extremely large dispersion does not occur in a potential of each pixel capacitor with respect to a potential of the data signal line S, so that it is possible to restrict dispersion of a leak current flowing via an active element of each pixel. Thus, potential variation of a pixel PIX is reduced, so that it is possible to improve display quality during a non-scanning period. That is, in an active-matrix-type liquid crystal display, when a frame frequency is reduced by setting the non-scanning period to be sufficiently larger than a scanning period while a standby image is being displayed so as to realize low power consumption, the display quality is improved.

Abstract: The scanning signal line driving circuit sequentially carries out active driving with respect to each set of a certain number of scanning signal lines which are adjacent to each other in a vertical direction, and when carrying out an actual writing with respect to a first set of a certain number of pixel lines adjacent to each other in the vertical direction, carries out pre-charging with respect to a second set of the certain number of pixel lines to which the actual writing is carried out next with a potential of a same polarity as that of the first set of the certain number of pixel lines. In this manner, it is possible to provide a matrix image display device with no irregularities in display quality and is capable of matching the apparent vertical resolution of the device to that of the image source, when using an image signal of vertical resolution lower than the maximum physical vertical resolution of the device.

Abstract: A precharge control circuit constituted by (1) a latch circuit mounted in a precharge circuit and (2) a level shifter circuit of a current drive type controlled through an output of the latch circuit is included. The precharge control circuit changes the latch circuit to an active state to cause the level shifter circuit of a current drive type to operate only during a precharge period and also during immediately preceding and succeeding periods, and outside these periods, changes the latch circuit in a non-active state and the level shifter circuit of a current drive type in an operating state to save power consumption in the level shifter circuit. This enables a low-power-consuming precharge circuit, as well as a low-power-consuming image display device with a high quality display capability, to be offered.

Abstract: An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.