Abstract: A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The switching circuit further includes a gate voltage generating circuit configured to switch voltage applied to the gate of the PLDMOS between a first voltage and a second voltage, wherein the first voltage is substantially the same as an input voltage from the converting circuit, and wherein a difference between the first voltage and the second voltage is lower than the gate-source breakdown voltage of the PLDMOS.

Abstract: A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The switching circuit further includes a gate voltage generating circuit configured to switch voltage applied to the gate of the PLDMOS between a first voltage and a second voltage, wherein the first voltage is substantially the same as an input voltage from the converting circuit, and wherein a difference between the first voltage and the second voltage is lower than the gate-source breakdown voltage of the PLDMOS.

Abstract: A body-bias voltage controller includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal.

Abstract: A level shift circuit including a level conversion unit that converts an input signal having a signal level of a first voltage into a signal having a signal level of a second voltage that is higher than the first voltage. The level conversion unit includes first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, which differs from the first conductivity type and of which switching is controlled in accordance with the input signal. The third and fourth MOS transistors include drains supplied with the second voltage via the first and second MOS transistors, respectively. A control unit, when detecting a decrease in the first voltage, controls a body bias of the third and fourth MOS transistors to decrease a threshold voltage of the third and fourth MOS transistors.

Abstract: A level shift circuit including a level conversion unit that converts an input signal having a signal level of a first voltage into a signal having a signal level of a second voltage that is higher than the first voltage. The level conversion unit includes first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, which differs from the first conductivity type and of which switching is controlled in accordance with the input signal. The third and fourth MOS transistors include drains supplied with the second voltage via the first and second MOS transistors, respectively. A control unit, when detecting a decrease in the first voltage, controls a body bias of the third and fourth MOS transistors to decrease a threshold voltage of the third and fourth MOS transistors.

Abstract: A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents.

Abstract: A body-bias voltage controller includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal.

Abstract: A level shift circuit determining a logic value while preventing load capacitance from increasing. A voltage detector detects the states of first and second voltages and generates first and second detection signals. A first logic unit generates a first control signal having a level that is in accordance with an input signal or a level of a third voltage in response to the first detection signal. A second logic unit generates a second control signal having a level that is in accordance with the first control signal or a level of the second voltage in response to the second detection signal. A level converter generates an output signal based on the first and second control signals and clamps the output signal at a fixed level when an abnormality occurs in the first voltage.

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carry out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will resent a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract: A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential power supply and which is normally inactivated and generates a first leak current, at least one N-channel MOS transistor which is coupled between a low potential power and at least the one P-channel MOS transistor and which is normally inactivated and generates a second leak current, and a detector which detects a potential generated at a node between the at least one P-channel MOS transistor and the at least one N-channel MOS transistor in accordance with the first and second leak currents.

Abstract: An excluding unit is controlled by a control signal received from a control unit, and based on the control signal a determination is made for each of circuit blocks as to whether either a voltage signal at a position of its corresponding circuit block or a signal indicating a voltage is outputted to a selection unit. From a circuit block which is not in operation, the voltage, but not a voltage signal at a position of the circuit block, is outputted to the selection unit. By this, the circuit block which is not in operation cannot be judged to have voltage drop, and accordingly, a high supply voltage cannot be supplied. Consequently, a malfunction caused by supply voltages to other circuit blocks being too high does not occur.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4.

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract: It is an object of the present invention to provide a semiconductor device design method and program that can rapidly improve power supply noise characteristics and reduce the noise sufficiently without being restricted in design and noise solution. A step of performing frequency analysis on a power supply distribution network model creates a power supply distribution network model based on electric characteristics obtained in accordance with specifications (maximum allowable drop value of power supply voltage, power supply current value, operating frequency, etc.) of the semiconductor device and performs frequency analysis on this power supply distribution network model. A step of performing frequency analysis based on an operating current waveform analyzes power supply current characteristics based on an operating current waveform obtained in accordance with the specification.

Abstract: A level shift circuit determining a logic value while preventing load capacitance from increasing. A voltage detector detects the states of first and second voltages and generates first and second detection signals. A first logic unit generates a first control signal having a level that is in accordance with an input signal or a level of a third voltage in response to the first detection signal. A second logic unit generates a second control signal having a level that is in accordance with the first control signal or a level of the second voltage in response to the second detection signal. A level converter generates an output signal based on the first and second control signals and clamps the output signal at a fixed level when an abnormality occurs in the first voltage.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: An excluding unit is controlled by a control signal received from a control unit, and based on the control signal a determination is made for each of circuit blocks as to whether either a voltage signal at a position of its corresponding circuit block or a signal indicating a voltage is outputted to a selection unit. From a circuit block which is not in operation, the voltage, but not a voltage signal at a position of the circuit block, is outputted to the selection unit. By this, the circuit block which is not in operation cannot be judged to have voltage drop, and accordingly, a high supply voltage cannot be supplied. Consequently, a malfunction caused by supply voltages to other circuit blocks being too high does not occur.